An analytical model for breakdown voltage of surface implanted SOI RESURF LDMOS

IEEE Transactions on Electron Devices

Volumn 47, Issue 5, 2000, Pages 1006-1009

  Chung, Sang Koo ^a  

^a Ajou University   (South Korea)

Author keywords

Breakdown voltage; Modeling; On resistance; Surface implanted SOI RESURF LDMOS

Indexed keywords

EID: 0000702486     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.841233     Document Type: Article

References (6)

1. G. Charitat, H. Tranduc, P. Granadel, and P. Rössel, "Improvement of the on resistance of power VDMOS by surface doping: Effect on the breakdown voltage," Microelectron. J., vol. 21, pp. 21-27, Dec. 1990.
2. G. Charitat, M. A. Bouanane, and P. Rössel, "A new junction termination technique for power devices: RESURF LDMOS with SIPOS layers," in Proc. 4th ISPSD, 1992, pp. 213-216.
3. S. K. Chung et al., "Analytical model for minimum drift region length of SOI RESURF diodes," IEEE Electron Device Lett., vol. 17,no. 1,pp. 22-24, 1996.
4. W. Fulop, "Calculation of avalanche breakdown of silicon p-n junction," Solid-State Electron., vol. 10, pp. 39-43, 1967.
5. S. K. Chung and S. Y. Han, "Analytical model for the surface field distribution of SOI RESURF devices," IEEE Trans. Electron Devices, vol. 45, pp. 1374-1376, June 1998.
6. R. Held, J. Serafin, M. Fuellmann, R. Constapel, and J. Korec, "Investigation of static and dynamic characteristics of SOI-LDMOSFET's passivated with semi-insulating layers," in Proc. 5th ISPSD, 1993, pp. 130-134.