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Volumn 53, Issue 11, 2004, Pages 1497-1503

A measure of quality for n-detection test sets

Author keywords

N detection tests; Test set ordering; Unmodeled faults

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; FAULT TOLERANT COMPUTER SYSTEMS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SET THEORY; STATISTICAL TESTS;

EID: 8744236029     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2004.87     Document Type: Article
Times cited : (47)

References (8)
  • 1
    • 0029510949 scopus 로고
    • "An Experimental Chip to Evaluate Test Techniques Experiment Results"
    • Oct
    • S.C. Ma, P. Franco, and E.J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experiment Results," Proc. 1995 Int'l Test Conf., pp. 663-672, Oct. 1995.
    • (1995) Proc. 1995 Int'l Test Conf. , pp. 663-672
    • Ma, S.C.1    Franco, P.2    McCluskey, E.J.3
  • 4
    • 0035684196 scopus 로고    scopus 로고
    • "Multiple-Output Propagation Transition Fault Test"
    • Oct
    • C.-W. Tseng and E.J. McCluskey, "Multiple-Output Propagation Transition Fault Test," Proc. Int'l Test Conf., pp. 358-366, Oct. 2001.
    • (2001) Proc. Int'l Test Conf. , pp. 358-366
    • Tseng, C.-W.1    McCluskey, E.-J.2
  • 5
    • 0034476103 scopus 로고    scopus 로고
    • "Enhanced DO-RE-ME Based Defect Level Prediction Using Defect Site Aggregation-MPG-D"
    • Oct
    • J. Dworak, M.R. Grimaila, S. Lee, L.-C. Wang, and M.R. Mercer, " Enhanced DO-RE-ME Based Defect Level Prediction Using Defect Site Aggregation-MPG-D," Proc. Int'l Test Conf., pp. 930-939, Oct. 2000.
    • (2000) Proc. Int'l Test Conf. , pp. 930-939
    • Dworak, J.1    Grimaila, M.R.2    Lee, S.3    Wang, L.-C.4    Mercer, M.R.5
  • 7
    • 0035684323 scopus 로고    scopus 로고
    • "On Static Test Compaction and Test Pattern Ordering for Scan Designs"
    • Oct
    • X. Lin, J. Rajski, I. Pomeranz, and S.M. Reddy, "On Static Test Compaction and Test Pattern Ordering for Scan Designs," Proc. Int'l Test Conf., pp. 1088-1097, Oct. 2001
    • (2001) Proc. Int'l Test Conf. , pp. 1088-1097
    • Lin, X.1    Rajski, J.2    Pomeranz, I.3    Reddy, S.M.4
  • 8
    • 0032664178 scopus 로고    scopus 로고
    • "Defect-Oriented Test Scheduling"
    • Apr
    • W. Jiang and B. Vinnakota, "Defect-Oriented Test Scheduling," Proc. VLSI Test Syrup., pp. 433-438, Apr. 1999.
    • (1999) Proc. VLSI Test Syrup. , pp. 433-438
    • Jiang, W.1    Vinnakota, B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.