Comparator trees for winner-take-all circuits

Neurocomputing

Volumn 62, Issue 1-4, 2004, Pages 389-403

  Hendry, D C ^a  

^a UNIVERSITY OF ABERDEEN   (United Kingdom)

Author keywords

Comparator trees; Hardware implementations; Self organising map; Winner take all

Indexed keywords

COMPUTER ARCHITECTURE; NEURAL NETWORKS; SELF ORGANIZING MAPS; TREES (MATHEMATICS);

DIGITAL IMPLEMENTATION; MULTIPLEXOR ARCHITECTURES; PROPAGATION DELAYS;

DIGITAL CIRCUITS;

ALGORITHM; ARTICLE; ARTIFICIAL NEURAL NETWORK; CALCULATION; CONTROLLED STUDY; DATA ANALYSIS; DIGITAL COMPUTER; INTERMETHOD COMPARISON; LOGIC; MATHEMATICAL COMPUTING; MATHEMATICAL PARAMETERS; PRIORITY JOURNAL; REGULATORY MECHANISM;

EID: 8644287399     PISSN: 09252312     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.neucom.2004.05.002     Document Type: Article

References (14)

1. Bhatnagar H. Advanced ASIC Chip Synthesis 1999 Kluwer Academic Publishers Dordrecht
2. Cavanagh J. Digital Computer Arithmetic: Design and Implementation 1984 McGraw-Hill New York
3. Hendry D. Duncan A. Lightowler N. IP core implementation of a self-organising neural network IEEE Trans. Neural Networks 14 5 2003 1085-1096
4. Keating M. Bricaud P. Reuse Methodology Manual 1999 Kluwer Academic Publishers Dordrecht
5. T. Kohonen, Self-Organizing Maps, 3rd Edition, Springer Series in Information Sciences, Springer, Berlin, 2001
6. Leiserson C. Saxe J.B. Retiming synchronous circuitry Algorithmica 6 1 1991 5-35
7. N. Lightowler, Modular maps: An implementation strategy for the self-organizing map, Ph.D. Thesis, University of Aberdeen, 1997.
8. N. Lightowler, A. Allen, H. Grant, D. Hendry, T. Spracklen, The modular map, in: Neural Networks, IJCNN'99, Vol. 2, 1999, pp. 851-856
9. Mailachalam B. Srikanthan T. Area-time issues in the VLSI implementation of self organizing map neural networks Microprocess. Microsystems 26 2002 399-406
10. M. Ogawa, K. Ito, T. Shibata, A general-purpose vector-quantisation processor employing two-dimensional bit-propagating winner-take-all, in: VLSI Circuits Digest of Technical Papers, 2002, pp. 244-247
11. U. Ruckert, ULSI architectures for artificial neural networks, IEEE Micro (2002) 10-19
12. Ruping S. Porrman M. Ruckert U. SOM accelerator systems Neurocomputing 21 1998 31-50
13. Shenoy N. Retiming: Theory and practice Integr. VLSI J. 22 1-2 1997 1-21
14. R. Tawel, N. Aranki, G. Puskorius, K. Marco, L. Feldkamp, J. James, G. Jesion, T. Feldkamp, Custom VLSI ASIC for automotive applications with recurrent networks, in: Neural Networks Proceedings, IEEE World Congress on Computational Intelligence, Vol. 1, IEEE, New York, 1998, pp. 598-602