SOM accelerator system

Neurocomputing

Volumn 21, Issue 1-3, 1998, Pages 31-50

  Ruping S ^a   Porrmann, M ^a   Ruckert U ^a  

^a UNIVERSITY OF PADERBORN   (Germany)

Author keywords

Hardware accelerator; Neural hardware system; Self organizing maps; VLSI Design

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS; MICROPROCESSOR CHIPS; VECTORS; VLSI CIRCUITS;

SELF-ORGANIZING MAP (SOM) ACCELERATOR;

NEURAL NETWORKS;

ARTICLE; ASSOCIATIVE MEMORY; COMPUTER ANALYSIS; COMPUTER PROGRAM; COMPUTER SIMULATION; COMPUTER SYSTEM; INTEGRATED CIRCUIT; MATHEMATICAL COMPUTING; NERVE CELL NETWORK; NEUROLOGY; POWER SUPPLY; PRIORITY JOURNAL; SEMICONDUCTOR;

EID: 0344110442     PISSN: 09252312     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0925-2312(98)00042-3     Document Type: Article

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