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Volumn 22, Issue 1-2, 1997, Pages 1-21

Retiming: Theory and practice

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; ELECTRIC NETWORK SYNTHESIS; OPTIMIZATION; POLYNOMIALS;

EID: 0031197857     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(97)00002-3     Document Type: Article
Times cited : (35)

References (50)
  • 6
    • 0025794584 scopus 로고
    • Synchronous logic synthesis: Algorithms for cycle-time minimization
    • G.de. Micheli, Synchronous logic synthesis: Algorithms for cycle-time minimization, IEEE Trans. Comput. Aided Des. (1991) 63-73.
    • (1991) IEEE Trans. Comput. Aided Des. , pp. 63-73
    • Micheli, G.De.1
  • 9
    • 0026121396 scopus 로고
    • Partitioning sequential circuits for logic synthesis
    • S. Dey, F. Brglez, G. Kedem, Partitioning sequential circuits for logic synthesis, IEEE J. of Solid-State Circuits 26(3) (1991) 350-360.
    • (1991) IEEE J. of Solid-state Circuits , vol.26 , Issue.3 , pp. 350-360
    • Dey, S.1    Brglez, F.2    Kedem, G.3
  • 13
    • 0025464163 scopus 로고
    • Clock skew optimization
    • J. Fishburn, Clock skew optimization, IEEE Trans. Comput. 39 (1990) 945-951.
    • (1990) IEEE Trans. Comput. , vol.39 , pp. 945-951
    • Fishburn, J.1
  • 16
    • 0029720742 scopus 로고    scopus 로고
    • Architectural retiming: Pipelining latency-constrained circuits
    • S. Hassoun, C. Ebeling, Architectural retiming: Pipelining latency-constrained circuits, in: Proc. Design Automation Conf. 1996, pp. 708-713.
    • (1996) Proc. Design Automation Conf. , pp. 708-713
    • Hassoun, S.1    Ebeling, C.2
  • 17
    • 0027868455 scopus 로고
    • Retiming gated clocks and precharged circuit structures
    • A.T. Ishii, Retiming gated clocks and precharged circuit structures, in: Proc. Internat. Conf. Computer-Aided Design, 1993, pp. 300-307.
    • (1993) Proc. Internat. Conf. Computer-aided Design , pp. 300-307
    • Ishii, A.T.1
  • 26
    • 0026005478 scopus 로고
    • Retiming synchronous circuitry
    • C.E. Leiserson, J.B. Saxe, Retiming synchronous circuitry, Algorithmica 6(1) (1991) 5-35.
    • (1991) Algorithmica , vol.6 , Issue.1 , pp. 5-35
    • Leiserson, C.E.1    Saxe, J.B.2
  • 28
    • 0042415586 scopus 로고
    • Optimal retiming of multi-phase level-clocked circuits
    • B. Lockyear, C. Ebeling, Optimal retiming of multi-phase level-clocked circuits, Adv. Res. VLSI (1992).
    • (1992) Adv. Res. VLSI
    • Lockyear, B.1    Ebeling, C.2
  • 30
    • 0027880690 scopus 로고
    • The practical application of retiming to the design of high-performance systems
    • B.E. Lockyear, C. Ebeling, The practical application of retiming to the design of high-performance systems, in: Proc. Internat. Conf. Computer-Aided Design, 1993, pp. 288-295.
    • (1993) Proc. Internat. Conf. Computer-aided Design , pp. 288-295
    • Lockyear, B.E.1    Ebeling, C.2
  • 35
    • 0027839672 scopus 로고
    • Retiming by combination of relocation and clock delay adjustment
    • H.-G. Martin, Retiming by combination of relocation and clock delay adjustment, in: Proc. European Design Automation Conf. 1993, pp. 384-389.
    • (1993) Proc. European Design Automation Conf. , pp. 384-389
    • Martin, H.-G.1
  • 38
    • 0029720913 scopus 로고
    • Optimal clock period technology mapping for FPGA circuits
    • P. Pan, C.L. Liu, Optimal clock period technology mapping for FPGA circuits, in: Proc. Design Automation Conf. 1995, pp. 720-725.
    • (1995) Proc. Design Automation Conf. , pp. 720-725
    • Pan, P.1    Liu, C.L.2
  • 39
  • 46
    • 0028725871 scopus 로고
    • Retiming with non-zero clock skew, variable register and interconnect delay
    • New York
    • T. Soyata, E. Friedman, Retiming with non-zero clock skew, variable register and interconnect delay, in: Proc. Internat. Conf. on Computer-Aided Design, IEEE, New York, 1994, pp. 234-241.
    • (1994) Proc. Internat. Conf. on Computer-aided Design, IEEE , pp. 234-241
    • Soyata, T.1    Friedman, E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.