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Volumn 26, Issue 9-10, 2002, Pages 399-406

Area-time issues in the VLSI implementation of self organizing map neural networks

Author keywords

Content addressable memories; Self organizing map neural networks; Vector quantization

Indexed keywords

ASSOCIATIVE STORAGE; OPTIMAL SYSTEMS; REAL TIME SYSTEMS; VECTOR QUANTIZATION; VLSI CIRCUITS;

EID: 0037147586     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0141-9331(02)00065-0     Document Type: Article
Times cited : (23)

References (15)
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    • Kohonen, T.1
  • 4
    • 0032049194 scopus 로고    scopus 로고
    • Color image compression and limited display using self-organization Kohonen map
    • Pei S.-C., Lo Y.-S. Color image compression and limited display using self-organization Kohonen map. IEEE Trans. Circuits Syst. 8:(2):1998;191-205.
    • (1998) IEEE Trans. Circuits Syst. , vol.8 , Issue.2 , pp. 191-205
    • Pei, S.-C.1    Lo, Y.-S.2
  • 5
    • 0021412027 scopus 로고
    • Vector quantization
    • Gray R.M. Vector quantization. IEEE ASSP Mag. 1:(2):1984;4-29.
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    • Gray, R.M.1
  • 7
    • 0015401565 scopus 로고
    • Some computer organizations and their effectiveness
    • Flynn M.J. Some computer organizations and their effectiveness. IEEE Trans. Computers. C-21:(9):1972.
    • (1972) IEEE Trans. Computers , vol.C-21 , Issue.9
    • Flynn, M.J.1
  • 9
    • 0028501883 scopus 로고
    • A VLSI architecture for a real-time code book generator and encoder of a vector quantizer
    • Tsang K., Wei W.Y. A VLSI architecture for a real-time code book generator and encoder of a vector quantizer. IEEE Trans. VLSI Syst. 2:(3):1994;360-364.
    • (1994) IEEE Trans. VLSI Syst. , vol.2 , Issue.3 , pp. 360-364
    • Tsang, K.1    Wei, W.Y.2
  • 12
    • 0029220521 scopus 로고
    • How to modify Kohonen's self-organising feature maps for an efficient digital parallel implementation
    • Vassilas N., Thiran P., Ienne P. How to modify Kohonen's self-organising feature maps for an efficient digital parallel implementation. Proc. Fourth Int. Conf. Artif. Neural Networks. 1995;86-91.
    • (1995) Proc. Fourth Int. Conf. Artif. Neural Networks , pp. 86-91
    • Vassilas, N.1    Thiran, P.2    Ienne, P.3
  • 13
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    • Efficient embeddings of binary trees in VLSI arrays
    • September
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    • Gordon, D.1
  • 15
    • 0019007733 scopus 로고
    • The binary tree as an interconnection network: Applications to multiprocessor systems and VLSI
    • Horowitz E., Zorat A. The binary tree as an interconnection network: applications to multiprocessor systems and VLSI. IEEE Trans. Computers. C-30:1981;247-253.
    • (1981) IEEE Trans. Computers , vol.C-30 , pp. 247-253
    • Horowitz, E.1    Zorat, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.