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Volumn 4, Issue , 1999, Pages 1945-1948

A NEW SCALABLE DSP ARCHITECTURE FOR SYSTEM ON CHIP (SOC) DOMAINS

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; DIGITAL SIGNAL PROCESSORS; PROGRAMMABLE LOGIC CONTROLLERS; REQUIREMENTS ENGINEERING; SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 85056930934     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.1999.758306     Document Type: Conference Paper
Times cited : (11)

References (12)
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    • Proc. OfDAC '97 , vol.97 , pp. 353-358
    • Kim, K.1    Karri, R.2    Potkonjak, M.3
  • 2
    • 33645150188 scopus 로고    scopus 로고
    • HiPAR-DSP: A parallel VLIW RISC processor for real time image processing applications
    • J. Wittenburg et al, "HiPAR-DSP: A parallel VLIW RISC processor for real time image processing applications," in Proc. ofICA3PP '97, pp. 155-162, 1997.
    • (1997) Proc. ofICA3PP '97 , pp. 155-162
    • Wittenburg, J.1
  • 3
    • 0031640356 scopus 로고    scopus 로고
    • A memory system supporting the efficient SIMD computation of the two dimensional DWT
    • M. Trenas, J. Lopez, and E. L-Zapata, "A memory system supporting the efficient SIMD computation of the two dimensional DWT," in Proc. oflCASSP '98, 1998.
    • (1998) Proc. OflCASSP '98
    • Trenas, M.1    Lopez, J.2    L-Zapata, E.3
  • 4
    • 3743061467 scopus 로고    scopus 로고
    • MicroUnity's mediaprocessor architecture
    • Aug
    • C. Hansen, "MicroUnity's mediaprocessor architecture," IEEE Micro, vol. 16, pp. 34-40, Aug 96.
    • (1996) IEEE Micro , vol.16 , pp. 34-40
    • Hansen, C.1
  • 5
    • 85188251203 scopus 로고    scopus 로고
    • Design methodology for digital signal processing
    • Zurich, Switzerland
    • G. Fettweis, "Design methodology for digital signal processing," in Proc. of ASAP '97, (Zurich, Switzerland), 97.
    • (1997) Proc. of ASAP '97
    • Fettweis, G.1
  • 6
    • 0031634870 scopus 로고    scopus 로고
    • An architectural study of a digital signal processor for block codes
    • (Seattle, WA, USA), May
    • W. Drescher, M. Mennenga, and G. Fettweis, "An architectural study of a digital signal processor for block codes," in Proc. oflCASSP '98, vol. 5, (Seattle, WA, USA), pp. 3129-3133, May 98.
    • (1998) Proc. OflCASSP '98 , vol.5 , pp. 3129-3133
    • Drescher, W.1    Mennenga, M.2    Fettweis, G.3
  • 7
    • 0030711146 scopus 로고    scopus 로고
    • DSP cores for mobile communications: Where are we going ?
    • G. P. Fettweis, "DSP cores for mobile communications: Where are we going ?," in Proc.of ICASSP 97, vol. 1, pp. 279-/283, 97.
    • (1997) Proc.Of ICASSP 97 , vol.1 , pp. 279-283
    • Fettweis, G.P.1
  • 8
    • 0030682350 scopus 로고    scopus 로고
    • A structural approach for designing performance enhanced DSPs: 1-MIPS GSM fullrate vocoder case-study
    • IEEE, Apr
    • M. H. Weiss, U. Walther, and G. P. Fettweis, "A structural approach for designing performance enhanced DSPs: 1-MIPS GSM fullrate vocoder case-study," in Proc. of ICASSP 97, vol. 5, pp. 4085-4088, IEEE, Apr 1997.
    • (1997) Proc. of ICASSP 97 , vol.5 , pp. 4085-4088
    • Weiss, M.H.1    Walther, U.2    Fettweis, G.P.3
  • 9
    • 84889029941 scopus 로고    scopus 로고
    • Using loop transformations to optimize memory accesses and register allocation in ASDSPs
    • Feb
    • M. Weiss et al, "Using loop transformations to optimize memory accesses and register allocation in ASDSPs," in Proc. ofSDA98, pp. 9-17, Feb 98.
    • (1998) Proc. ofSDA98 , pp. 9-17
    • Weiss, M.1
  • 11
    • 0003726367 scopus 로고    scopus 로고
    • A block-floating-point system for multiple datapath DSP
    • (Boston, MA, USA), Oct.
    • S. Kobajashi and G. P. Fettweis, "A block-floating-point system for multiple datapath DSP," in Proc. of SiPS '98, (Boston, MA, USA), Oct. 1998.
    • (1998) Proc. of SiPS '98
    • Kobajashi, S.1    Fettweis, G.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.