Structural approach for designing performance enhanced signal processors: A 1-MIPS GSM fullrate vocoder case study

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 5, Issue , 1997, Pages 4085-4088

  Weiss, Matthias H ^a   Walther, Ulrich ^a   Fettweis, Gerhard P ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; PIPELINE PROCESSING SYSTEMS; RANDOM ACCESS STORAGE; REDUCED INSTRUCTION SET COMPUTING;

GROUP SPECIAL MOBILE (GSM) FULLRATE VOCODER; TAGGED VERY LONG INSTRUCTION WORD INSTRUCTION SET ARCHITECTURE;

VOCODERS;

EID: 0030682350     PISSN: 07367791     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)