An architectural study of a digital signal processor for block codes

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 5, Issue , 1998, Pages 3129-3132

  Drescher, Wolfram ^a   Mennenga, Menno ^a   Fettweis, Gerhard ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL STUDIES; DECODING ALGORITHM; DIGITAL SIGNAL PROCESSORS (DSP); DOMAIN SPECIFIC; FAST DECODING;

DECODING; DIGITAL SIGNAL PROCESSORS; INTERACTIVE COMPUTER SYSTEMS; REAL TIME SYSTEMS;

SIGNAL PROCESSING;

EID: 0031634870     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.1998.678189     Document Type: Conference Paper

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