Predictable cache coherence for multi-core real-time systems

Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS

Volumn , Issue , 2017, Pages 235-246

  Hassan, Mohamed ^a   Kaushik, Anirudh M ^a   Patel, Hiren ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; DISTRIBUTED COMPUTER SYSTEMS;

ARCHITECTURAL CHANGES; CACHE COHERENCE; CACHE COHERENCE PROTOCOLS; COHERENCE STATE; LATENCY BOUNDS; MULTI-CORE SYSTEMS; SYNTHETIC WORKLOADS; WORST-CASE LATENCIES;

REAL TIME SYSTEMS;

EID: 85021831674     PISSN: 15453421     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2017.13     Document Type: Conference Paper

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