Extended performance analysis of the time predictable on-demand coherent data cache for multi-and many-core systems

Proceedings - International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2014

Volumn , Issue , 2014, Pages 107-114

  Pyka, Arthur ^a   Rohde, Mathias ^a   Uhrig, Sascha ^a  

^a TU DORTMUND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; EMBEDDED SYSTEMS; INTERACTIVE COMPUTER SYSTEMS;

CACHE ANALYSIS; CACHE SYSTEMS; COHERENCE PROTOCOL; COHERENT DATA; EMBEDDED REAL TIME SYSTEMS; EXTENDED PERFORMANCE; TIME PREDICTABILITIES; WORST-CASE EXECUTION TIME ANALYSIS;

REAL TIME SYSTEMS;

EID: 84907890690     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SAMOS.2014.6893201     Document Type: Conference Paper

References (29)

1. A. Pyka, M. Rohde, and S. Uhrig, "A Real-time Capable Firstlevel Cache for Multi-cores," in Workshop on High Performance and Real-time Embedded Systems (HiRES) in conjunction with HiPEAC'13, Berlin, Germany, jan 2013. [Online]. Available: http://www.cister.isep.ipp.pt/hires2013/
2. -, "Performance evaluation of the time analysable on-demand coherent cache," in TrustCom/ISPA/IUCC, 2013, pp. 1887-1892.
3. A. Pyka, M. Rohde, P. G. Zaykov, and S. Uhrig, "Case Study: On-Demand Coherent Cache for Avionic Application," in 2nd Workshop on High Performance and Real-time Embedded Systems (HiRES) in conjunction with HiPEAC'14, Vienna, Austria, Jan 2014. [Online]. Available: http://www.cister.isep.ipp.pt/hires2014/
4. P. Stenstrom, "A survey of cache coherence schemes for multiprocessors," Computer, vol. 23, no. 6, pp. 12-24, Jun. 1990. [Online]. Available: http://dx.doi.org/10.1109/2.55497
5. M. Tomasevic and V. Milutinovic, "Hardware approaches to cache coherence in shared-memory multiprocessors, part 1," Micro, IEEE, vol. 14, no. 5, p. 52, oct. 1994.
6. OpenSPARC T2 Implementation Supplement, Hyperprivileged Edition, Sun Microsystems, Inc., Aug. 2007. [Online]. Available: http://www.opensparc.net/docs/OST2-UASuppl-current-draft-HPEXT. pdf
7. An Introduction to the Intel QuickPath Interconnect, Intel Corporation., Jan. 2007. [Online]. Available: http://www.intel.com/technology/quickpath/introduction
8. P. Conway, N. Kalyanasundharam, G. Donley, K. Lepak, and B. Hughes, "Cache hierarchy and memory subsystem of the amd opteron processor," Micro, IEEE, vol. 30, no. 2, pp. 16-29, march-april 2010.
9. D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C.-C. Miao, J. Brown, and A. Agarwal, "On-chip interconnection architecture of the tile processor," Micro, IEEE, vol. 27, no. 5, pp. 15-31, sept.-oct. 2007.
10. M. Ferdman, P. Lotfi-Kamran, K. Balet, and B. Falsafi, "Cuckoo directory: A scalable directory for many-core systems," in High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on, feb. 2011, pp. 169-180.
11. M. M. K. Martin, D. J. Sorin, A. Ailamaki, A. R. Alameldeen, R. M. Dickson, C. J. Mauer, K. E. Moore, M. Plakal, M. D. Hill, and D. A. Wood, "Timestamp snooping: an approach for extending smps," SIGARCH Comput. Archit. News, vol. 28, no. 5, pp. 25-36, Nov. 2000. [Online]. Available: http://doi.acm.org/10.1145/378995.378998
12. J. Zebchuk, V. Srinivasan, M. Qureshi, and A. Moshovos, "A tagless coherence directory," in Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on, dec. 2009, pp. 423-434.
13. S. Cho and L. Jin, "Managing distributed, shared l2 caches through oslevel page allocation," in Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, ser. MICRO 39. Washington, DC, USA: IEEE Computer Society, 2006, pp. 455-468.
14. C. Fensch and M. Cintra, "An os-based alternative to full hardware coherence on tiled cmps," in High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th International Symposium on, feb. 2008, pp. 355-366.
15. J. Jaehyuk Huh, C. Changkyu Kim, H. Shafi, L. Lixin Zhang, D. Burger, and S. Keckler, "A nuca substrate for flexible cmp cache sharing," Parallel and Distributed Systems, IEEE Transactions on, vol. 18, no. 8, pp. 1028-1040, aug. 2007.
16. J. H. Kelm, D. R. Johnson, W. Tuohy, S. S. Lumetta, and S. J. Patel, "Cohesion: a hybrid memory model for accelerators," in Proceedings of the 37th annual international symposium on Computer architecture, ser. ISCA '10. New York, NY, USA: ACM, 2010, pp. 429-440. [Online]. Available: http://doi.acm.org/10.1145/1815961.1816019
17. R. Sen and Y. N. Srikant, "Wcet estimation for executables in the presence of data caches," in Proceedings of the 7th ACM & IEEE International Conference on Embedded software, EMSOFT 2007, September 30-October 3, 2007, Salzburg, Austria, C. M. Kirsch and R. Wilhelm, Eds. ACM, 2007, pp. 203-212.
18. H. Ramaprasad and F. Mueller, "Bounding worst-case data cache behavior by analytically deriving cache reference patterns," in Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium, ser. RTAS '05. Washington, DC, USA: IEEE Computer Society, 2005, pp. 148-157. [Online]. Available: http://dx.doi.org/10.1109/RTAS.2005.12
19. I. Liu, J. Reineke, and E. Lee, "A pret architecture supporting concurrent programs with composable timing properties," in Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on, nov. 2010, pp. 2111-2115.
20. A. Asaduzzaman, N. Limbachiya, I. Mahgoub, and F. Sibai, "Evaluation of i-cache locking technique for real-time embedded systems," in Innovations in Information Technology, 2007. IIT '07. 4th International Conference on, nov. 2007, pp. 342-346.
21. H. Cheong, "Life span strategy-a compiler-based approach to cache coherence," in Proceedings of the 6th international conference on Supercomputing, ser. ICS '92. New York, NY, USA: ACM, 1992, pp. 139-148. [Online]. Available: http://doi.acm.org/10.1145/143369.143402
22. A. M. Molnos, S. D. Cotofana, M. J. Heijligers, and J. T. van Eijndhoven, "Throughput optimization via cache partitioning for embedded multiprocessors," in Embedded Computer Systems: Architectures, Modeling and Simulation, 2006. IC-SAMOS 2006. International Conference on, july 2006, pp. 185-191.
23. M. Eskicioglu, T. Marsland, W. Hu, and W. Shi, "Evaluation of the jiajia software dsm system on high performance computer architectures," in Systems Sciences, 1999. HICSS-32. Proceedings of the 32nd Annual Hawaii International Conference on, vol. Track8, 1999, p. 10.
24. A. Ros and S. Kaxiras, "Complexity-effective multicore coherence," in Proceedings of the 21st international conference on Parallel architectures and compilation techniques, ser. PACT '12. New York, NY, USA: ACM, 2012, pp. 241-252. [Online]. Available: http://doi.acm.org/10.1145/2370816.2370853
25. J. L. Hennessy and D. A. Patterson, Computer Architecture, Fourth Edition: A Quantitative Approach. San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 2006.
26. parMERASA-Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability, "http://www.parmerasa.eu/."
27. The SoCLib project. Mainpage, 2012. [Online]. Available: http://www.soclib.fr/
28. N. Anastopoulos, K. Nikas, G. Goumas, and N. Koziris, "Early experiences on accelerating dijkstra's algorithm using transactional memory," in Parallel Distributed Processing, 2009. IPDPS 2009. IEEE International Symposium on, May 2009, pp. 1-8.
29. N. Jasika, N. Alispahic, A. Elma, K. Ilvana, L. Elma, and N. Nosovic, "Dijkstra's shortest path algorithm serial and parallel execution performance analysis," in MIPRO, 2012 Proceedings of the 35th International Convention, May 2012, pp. 1811-1815.