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Volumn 1998-November, Issue , 1998, Pages 9-13

Static test compaction for IDDQ testing of sequential circuits

Author keywords

[No Author keywords available]

Indexed keywords

MICROSTRIP LINES; SEQUENTIAL CIRCUITS; TIMING CIRCUITS;

EID: 85011878537     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IDDQ.1998.730725     Document Type: Conference Paper
Times cited : (4)

References (12)
  • 2
    • 0002238418 scopus 로고
    • Circuit design for built-in current testing
    • Y. Miura and K. Kinoshita, "Circuit Design for Built-in Current Testing, " Proc. Int. Test Conf., pp.873-881, 1992.
    • (1992) Proc. Int. Test Conf. , pp. 873-881
    • Miura, Y.1    Kinoshita, K.2
  • 4
    • 0030381187 scopus 로고    scopus 로고
    • An efficient compact test generator for IDDQ testing
    • H. Kondo and K.-T. Cheng, "An Efficient Compact Test Generator for IDDQ Testing, " Proc. Asian Test Sym., pp.177-182, 1996.
    • (1996) Proc. Asian Test Sym. , pp. 177-182
    • Kondo, H.1    Cheng, K.-T.2
  • 5
    • 0032307486 scopus 로고    scopus 로고
    • A simple and efficient method for generating compact IDDQ test set for bridging faults
    • T. Shinogi and T. Hayashi, "A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Faults, " Proc. VLSI Test Symp., pp.112-117, 1997.
    • (1997) Proc. VLSI Test Symp. , pp. 112-117
    • Shinogi, T.1    Hayashi, T.2
  • 6
    • 0030399159 scopus 로고    scopus 로고
    • Driving toward higher IDDQ test quality for seuqnetial circuits: A generalized fault model and its ATPG
    • H. Kondo and K.-T. Cheng, "Driving Toward Higher IDDQ Test Quality for Seuqnetial Circuits: A Generalized Fault Model and Its ATPG, " Dig. Int. Conf. on Computer-Aided Design, pp.228-232, 1996.
    • (1996) Dig. Int. Conf. on Computer-Aided Design , pp. 228-232
    • Kondo, H.1    Cheng, K.-T.2
  • 8
    • 0343759492 scopus 로고
    • Simulation and generation of IDDQ tests for bridging faults in combinational circuits
    • S. Chakravarty and P. J. Thadikaran, "Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits, " Proc. VLSI Test Symp., pp.25-32, 1993.
    • (1993) Proc. VLSI Test Symp , pp. 25-32
    • Chakravarty, S.1    Thadikaran, P.J.2
  • 9
    • 0029713581 scopus 로고    scopus 로고
    • Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits
    • T. Lee, I. N. Hajj, E. M. Rundnick and J. H. Patel, "Genetic-Algorithm-Based Test Generation for Current Testing of Bridging Faults in CMOS VLSI Circuits, " Proc. VLSI Test Symp., pp.456-462, 1996.
    • (1996) Proc. VLSI Test Symp. , pp. 456-462
    • Lee, T.1    Hajj, I.N.2    Rundnick, E.M.3    Patel, J.H.4
  • 10
    • 0031356195 scopus 로고    scopus 로고
    • Sequential circuit test generation for iddq testing of bridging faults
    • Y. Higami, T. Maeda and K. Kinoshita, "Sequential Circuit Test Generation for IDDQ Testing of Bridging Faults, " Dig. Int. Workshop on IDDQ Testing, pp.12-16, 1997.
    • (1997) Dig. Int. Workshop on IDDQ Testing , pp. 12-16
    • Higami, Y.1    Maeda, T.2    Kinoshita, K.3
  • 12
    • 0027698840 scopus 로고
    • An efficient algorithm for sequential circuit test generation
    • T. P. Kelsey, K. K. Saluja and S. Y. Lee, "An Efficient Algorithm for Sequential Circuit Test Generation, " IEEE Trans. on Computers, vol.42, pp.1361-1371, 1993.
    • (1993) IEEE Trans. on Computers , vol.42 , pp. 1361-1371
    • Kelsey, T.P.1    Saluja, K.K.2    Lee, S.Y.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.