Simple and efficient method for generating compact IDDQ test set for bridging faults

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1998, Pages 112-117

  Shinogi, T ^a   Hayashi, T ^a  

^a MIE UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BRIDGING FAULTS;

EFFICIENCY; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT TESTING; ITERATIVE METHODS;

CMOS INTEGRATED CIRCUITS;

EID: 0032307486     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)