An Efficient compact test generator for IDDQtesting

Proceedings of the Asian Test Symposium

Volumn , Issue , 1996, Pages 177-182

  Kondo, H ^a   Cheng, K T ^a  

^a JFE STEEL CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; ELECTRIC FAULT CURRENTS; LOGIC DESIGN; LOGIC GATES; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS;

BRIDGING FAULTS; ESSENTIAL FAULT (EF); INPUT FAULT (IF) MODEL;

INTEGRATED CIRCUIT TESTING;

EID: 0030381187     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

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