Development of Low-Cost and Highly Reliable Wafer Process Package “WPP-2”

journal of the japan institute of electronics packaging

Volumn 5, Issue 3, 2002, Pages 264-271

  Kazama, Atsushi ^a   Satoh, Toshiya ^a   Yamaguchi, Yoshihide ^a   Anjoh, Ichiro ^a   Nishimura, Asao ^a  

^a HITACHI LTD   (Japan)

Author keywords

Finite Element Analysis; Reliability; Solder Joint; Temperature Cycling Test; Wafer Level Chip Size Package

Indexed keywords

EID: 85009644861     PISSN: 13439677     EISSN: 1884121x     Source Type: Journal    
DOI: 10.5104/jiep.5.264     Document Type: Article

References (6)

1. P. Garrou: “Wafer Level Chip Scale Packaging (WLCSP): An Overview”, IEEE Trans. Advanced Packaging, Vol. 23, No. 2, pp. 198-205, May, 2000.
2. T. Kawahara: “SuperCSPTM”, IEEE Trans. Advanced Packaging, Vol. 23, No. 2, pp. 215-219, 2000.
3. I. Kang, J. Kim, I. S. Park, K. Hur and S. Cho: “The Solder Joint and Runner Metal Reliability of Wafer-Level CSP(Omega-CSP)”, Proc. 50th Electronic Components and Technology Conf., Las Vegas, NV, pp. 87-92, 2000.
4. J. Lau and C. Chang: “Solder Joint Crack Propagation Analysis of Wafer-Level Chip Scale Package on Printed Circuit Board Assemblies”, Proc. 50th Electronic Components and Technology Conf., Las Vegas, NV, pp. 1360-1368, 2000.
5. Mate 2001, 7th Symposiumon “Microjoining and Assembly Technology in Electronics”, Yokohama, pp. 441-446, 2001.
6. M. Ahn, D. Lee, and S. Kang: “gOptimal Structure of Wafer Level Package for the Electrical Performance”, Proc. 50th Electronic Components and Technology Conf., Las Vegas, NV, pp. 530-534, 2000.