메뉴 건너뛰기




Volumn 2005, Issue , 2005, Pages 148-152

Debug support, calibration and emulation for multiple processor and powertrain control SoCs

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CALIBRATION; COMPUTER ARCHITECTURE; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; POWER CONTROL; PROGRAM DEBUGGING;

EID: 33646900740     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.109     Document Type: Conference Paper
Times cited : (31)

References (7)
  • 3
    • 0010361611 scopus 로고    scopus 로고
    • The economic impacts of inadequate infrastructure for software testing
    • National institute of standards and technology, US, May
    • U.S. Department of Commerce, The economic impacts of inadequate infrastructure for software testing, tech. report RTI-7007.011US, National institute of standards and technology, US, May 2002.
    • (2002) Tech. Report , vol.RTI-7007.011US
  • 6
    • 0034510954 scopus 로고    scopus 로고
    • Emerging on-chip debugging techniques for real-time embedded systems
    • Dec.
    • C. MacNamee, and D. Heffernan, "Emerging on-chip debugging techniques for real-time embedded systems", IEE Computing & Control Engineering Journal, vol. 11, no. 6, Dec. 2000, pp. 295-303.
    • (2000) IEE Computing & Control Engineering Journal , vol.11 , Issue.6 , pp. 295-303
    • MacNamee, C.1    Heffernan, D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.