A methodology for the rapid injection of transient hardware errors

IEEE Transactions on Computers

Volumn 45, Issue 8, 1996, Pages 881-891

  Yount, Charles R ^a,b   Siewiorek, Daniel P ^a,c  

^a IEEE

^b INTEL CORPORATION   (United States)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Fault tolerance; Hybrid fault emulation; IBM ROMP; Register transfer language modeling; Software implementedfault injection; Verilog modeling

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SYSTEM RECOVERY; COMPUTER TESTING; ERROR ANALYSIS; PROGRAM PROCESSORS; REDUCED INSTRUCTION SET COMPUTING;

FAULT INJECTION; HYBRID FAULT EMULATION; REGISTER TRANSFER LANGUAGE (RTL) FAULT MODEL; RISC ORIENTED MICRO PROCESSOR (ROMP); VERILOG MODEL;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 0030216035     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.536231     Document Type: Article

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