Throughput-optimized openCL-based FPGA accelerator for large-scale convolutional neural networks

FPGA 2016 - Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Volumn , Issue , 2016, Pages 16-25

  Suda, Naveen ^a   Chandra, Vikas ^c   Dasika, Ganesh ^c   Mohanty, Abinash ^a   Ma, Yufei ^a   Vrudhula, Sarma ^b   Seo, Jae Sun ^a   Cao, Yu ^a  

^a Arizona State University   (United States)

^b ARIZONA STATE UNIVERSITY   (United States)

^c ARM Inc   (United States)

Author keywords

Convolutional neural networks; FPGA; OpenCL; Optimization

Indexed keywords

ACCELERATION; COMPUTER HARDWARE; COMPUTER VISION; CONVOLUTION; ENERGY EFFICIENCY; FACE RECOGNITION; HARDWARE; HIGH LEVEL SYNTHESIS; IMAGE CLASSIFICATION; LOGIC GATES; NEURAL NETWORKS; OPTIMIZATION; REAL TIME SYSTEMS; RECONFIGURABLE HARDWARE; THROUGHPUT;

COMPUTATIONAL RESOURCES; COMPUTER VISION APPLICATIONS; CONVOLUTIONAL NEURAL NETWORK; HARDWARE ACCELERATORS; LOW-POWER CONSUMPTION; MULTIPLE CONVOLUTION; OPENCL; THROUGHPUT-OPTIMIZED;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84966471227     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2847263.2847276     Document Type: Conference Paper

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