Neuromorphic architectures for spiking deep neural networks

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2016-February, Issue , 2015, Pages 4.2.1-4.2.4

  Indiveri, Giacomo ^a   Corradi, Federico ^a   Qiao, Ning ^a  

^a UNIVERSITY OF ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER CIRCUITS; DIGITAL DEVICES; ELECTRON DEVICES; FEATURE EXTRACTION; HARDWARE; NETWORKS (CIRCUITS);

ANALOG NEURONS; ASYNCHRONOUS LOGIC CIRCUITS; CUSTOM HARDWARES; DEEP NEURAL NETWORKS; EVENT-BASED; FEATURE CLASSIFICATION; NEUROMORPHIC ARCHITECTURES; NEUROMORPHIC VLSI;

VLSI CIRCUITS;

EID: 84964088529     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2015.7409623     Document Type: Conference Paper

References (15)

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