Architecture and design of a high performance SRAM for SOC design

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 447-451

  Singh, S ^a   Azmi, S ^a   Agrawal, N ^a   Phani, P ^a   Rout, A ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); COMPUTER AIDED DESIGN; DESIGN; MEMORY ARCHITECTURE; PROGRAMMABLE LOGIC CONTROLLERS; RANDOM ACCESS STORAGE; STATIC RANDOM ACCESS STORAGE; SYSTEM-ON-CHIP;

CIRCUIT PARTITIONING; CRITICAL ISSUES; DEEP SUB-MICRON TECHNOLOGY; DESIGN TECHNIQUE; HIGH-SPEED MEMORY; MEASURED RESULTS; SENSE AMPLIFIER; TRANSISTOR SIZING;

INTEGRATED CIRCUIT DESIGN;

EID: 84962234440     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994961     Document Type: Conference Paper

References (5)

1. Isao FUKUSHI, et al., "A Low-Power SRAM Using Improved Charge Transfer Sense Amplifiers and a dual-Vth CMOS Circuit Scheme" Symp. On VLSI Circuits Digest of Technical Papers, pp. 142-145, 1998.
2. Bharadwaj S Amrutur and Mark A. Horowitz, "A replica Technique for Wordline and Sense Control in Low-Power SRAM's" IEEE journal of Solid State Circuits, vol. 33, pp 1208-1219, 1998.
3. Nobutaro Shibata and Morimura Hiroki, "A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM with Charge-Recycling Input/Output Buffers", IEEE Journal of Solid-State Circuits, Vol. 34, No. 6, pp. 866-877, June 1999.
4. Simon J. Lovett, Gary A. Gibbs, and Ashish Pancholy, "Yield and Matching Implications for Static RAM Memory Array Sense-Amplifier Design", IEEE journal of Solid State Circuits, Vol. 35, No. 8, pp. 1200-1204, August 2000.
5. Ming-Chuen Shiau and Chung-Yu Wu, "The Signal Delay in Inetrconnect Lines Considering the effects of Small Geometry CMOS invertoers", IEEE Transactions on Circuits and Systems, Vol. 37, N0. 3, pp. 420-425, March 1990.