Memory data organization for improved cache performance in embedded processor applications

ACM Transactions on Design Automation of Electronic Systems

Volumn 2, Issue 4, 1997, Pages 384-409

  Panda, Preeti Ranjan ^a   Dutt, Nikil D ^a   Nicolau, Alexandru ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Cache memory; Data cache; Memory synthesis; Performance; System design; System synthesis; Verification

Indexed keywords

EID: 0012901719     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/268424.268464     Document Type: Article

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