메뉴 건너뛰기




Volumn , Issue , 2000, Pages 7-15

Deadline handling in real-time distributed objects

Author keywords

deadline; guarantee; message triggered; object; real time; service time; time triggered; TMO

Indexed keywords

DISTRIBUTED COMPUTER SYSTEMS;

EID: 84961988054     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISORC.2000.839506     Document Type: Conference Paper
Times cited : (10)

References (33)
  • 4
    • 0030644743 scopus 로고    scopus 로고
    • Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences
    • June
    • S. Vajapeyam and T. Mitra. Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences. 24th Intl. Symp. on Comp. Arch., June 1997.
    • (1997) 24th Intl. Symp. on Comp. Arch.
    • Vajapeyam, S.1    Mitra, T.2
  • 8
    • 0003468743 scopus 로고
    • Dynamic flow instruction cache memory organized around trace segments independent of virtual address line
    • U.S. Patent Jan
    • A. Peleg and U. Weiser. Dynamic flow instruction cache memory organized around trace segments independent of virtual address line. U.S. Patent 5,381,533, Jan 1995.
    • (1995)
    • Peleg, A.1    Weiser, U.2
  • 9
    • 0030380559 scopus 로고    scopus 로고
    • Trace cache: A low latency approach to high bandwidth instruction fetching
    • Dec
    • E. Rotenberg, S. Bennett, and J. Smith. Trace cache: a low latency approach to high bandwidth instruction fetching. 29th Intl. Symp. on Microarch., Dec 1996.
    • (1996) 29th Intl. Symp. on Microarch.
    • Rotenberg, E.1    Bennett, S.2    Smith, J.3
  • 14
    • 0007997616 scopus 로고    scopus 로고
    • ARB: A hardware mechanism for dynamic reordering of memory references
    • May
    • M. Franklin and G. S. Sohi. ARB: A hardware mechanism for dynamic reordering of memory references. IEEE Transactions on Computers, 45(5):552-571, May 1996.
    • (1996) IEEE Transactions on Computers , vol.45 , Issue.5 , pp. 552-571
    • Franklin, M.1    Sohi, G.S.2
  • 15
    • 0029514936 scopus 로고
    • Disjoint eager execution: An optimal form of speculative execution
    • Dec
    • A. Uht and V. Sindagi. Disjoint eager execution: An optimal form of speculative execution. 28th Intl. Symp. on Microarch., Dec 1995.
    • (1995) 28th Intl. Symp. on Microarch.
    • Uht, A.1    Sindagi, V.2
  • 18
    • 0031605348 scopus 로고    scopus 로고
    • The potential for using thread-level data speculation to facilitate automatic parallelization
    • Feb
    • J. Steffan and T. Mowry. The potential for using thread-level data speculation to facilitate automatic parallelization. 4th Intl. Symp. on High Perf. Comp. Arch., Feb 1998.
    • (1998) 4th Intl. Symp. on High Perf. Comp. Arch.
    • Steffan, J.1    Mowry, T.2
  • 19
    • 0029182726 scopus 로고
    • Single-program speculative multithreading (spsm) architecture: Compiler-assisted fine-grained multithreading
    • P. Dubey, K. O'Brien, K. M. O'Brien, and C. Barton. Single-program speculative multithreading (spsm) architecture: Compiler-assisted fine-grained multithreading. PACT-95, 1995.
    • (1995) PACT-95
    • Dubey, P.1    O'Brien, K.2    O'Brien, K.M.3    Barton, C.4
  • 20
    • 0029727822 scopus 로고    scopus 로고
    • The superthreaded architecture: Thread pipelining with run-time data dependence checking and control speculation
    • J.-Y. Tsai and P.-C. Yew. The superthreaded architecture: Thread pipelining with run-time data dependence checking and control speculation. PACT-96. 1996.
    • (1996) PACT-96
    • Tsai, J.-Y.1    Yew, P.-C.2
  • 22
    • 0032659683 scopus 로고    scopus 로고
    • Reducing branch misprediction penalties via dynamic control Independence detection
    • June
    • Y. Chou, J. Fung. and J. Shen. Reducing branch misprediction penalties via dynamic control Independence detection. Intl. Conf. on Supercomputing, June 1999.
    • (1999) Intl. Conf. on Supercomputing
    • Chou, Y.1    Fung, J.2    Shen, J.3
  • 23
    • 0007993303 scopus 로고    scopus 로고
    • Dynamic hammock predication for non-predicated instruction set architectures
    • Oct
    • A. Klauser, T. Austin, D. Grunwald, and B. Calder. Dynamic hammock predication for non-predicated instruction set architectures. PACT-98, Oct 1998.
    • (1998) PACT-98
    • Klauser, A.1    Austin, T.2    Grunwald, D.3    Calder, B.4
  • 24
    • 0031594002 scopus 로고    scopus 로고
    • Improving trace cache effectiveness with branch promotion and trace packing
    • June
    • S. Patel, M. Evers, and Y. Patt. Improving trace cache effectiveness with branch promotion and trace packing. 25th Intl. Symp. on Comp. Arch., June 1998.
    • (1998) 25th Intl. Symp. on Comp. Arch.
    • Patel, S.1    Evers, M.2    Patt, Y.3
  • 25
    • 0019596071 scopus 로고
    • Trace scheduling: A technique for global microcode compaction
    • July
    • J. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers. C-30(7):478-490, July 1981.
    • (1981) IEEE Transactions on Computers , vol.C-30 , Issue.7 , pp. 478-490
    • Fisher, J.1
  • 26
    • 84962009700 scopus 로고
    • Trace selection for compiling large c application programs to microcode
    • Dec
    • W. Hwu and P. Chang. Trace selection for compiling large c application programs to microcode. 21st Intl. Symp. on Microarch., Dec 1988.
    • (1988) 21st Intl. Symp. on Microarch.
    • Hwu, W.1    Chang, P.2
  • 31


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.