Improving fault coverage in system tests

Proceedings - 6th IEEE International On-Line Testing Workshop

Volumn , Issue , 2000, Pages 207-213

  Sosnowski, J ^a  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

TESTING;

COMMERCIAL OFF THE SHELVES; FAULT COVERAGES; HARDWARE COMPLEXITY; IN-SYSTEM TEST; ONLINE MONITORING; SYSTEM ENVIRONMENT; TEST EFFECTIVENESS; TEST PROCESS;

DESIGN FOR TESTABILITY;

EID: 84960402225     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2000.856638     Document Type: Conference Paper

References (16)

1. M. Abramovici, M.A. Breuer and A.D. Friedman, Digital system testing and testability design, Computer Science Press, New York, 1998.
2. R. C. Aitken, Nanometer technology effects on fault models for IC testing, IEEE Computer, vol. 32, no.11, Nov. 1999, pp.46-51.
3. K. Batcher, Ch. Papachristou, Instruction randomization self test for processor cores, Proc of IEEE VLSI Test Symposium, 1999, 34-40.
4. R. David, Random testing of digital circuits, Marcel Dekker Inc., 1998.
5. E.P. Duarte, T. A. Nanya, A hierarchical adaptive distributed system-level diagnosis algorithm, IEEE Transactions on Computers, vol.43, no.1 January, 1998, pp.34-45.
6. J. Hirase, S. Yoshimura, T. Sezaki, Automatic test pattern generation for improving the fault coverage of microprocessors, Proc. of Asian Test Symposium, 1999, pp.13-19.
7. M. H. Konijnenburg, J. T. van der Linden, A. J. van de Goor, Testability of the Philips 80C51 microcontroller, Proc. of IEEE International Test Conference, 1999, pp.820-829.
8. S. Mueller, Upgrading and repairing PCS, Que Corporation, 1998.
9. C. Pyron et al., DFT advances in Motoroal's MPC7400, a Power PC microprocessor, Proc. of IEEE International Test Conference, 1999, pp.137-146.
10. T. Shanley, Pentium Pro and Pentium II System Architecture, Addison, Weseley, New York, 1998.
11. D. Sima, T. Fountain, P. Kacsuk, Advanced computer architectures, Addison Wesley, Edingburgh, 1997.
12. J. Sosnowski, In system testing of cache memories, Proc. of IEEE International Test Conference, 1995, pp.384-393.
13. J. Sosnowski, A. Kusmierczyk, Pseudorandom versus deterministic testing of Intel 80x86 processors, Proc of Euromicro Conference, IEEE Computer Society, 1996, pp.329-336.
14. J. Sosnowski, P. Gawkowski, Tracing fault effects in system environment, Proc. of Euromicro Conference, IEEE Computer Society., 1999, pp.481-486.
15. J. Sosnowski, M. Hankus, Using IEEE1149.1 interface in systes with FPGAs, Proc. of IFAC Workshop on Programmable Devices and Systems, 2000, pp. 146-151.
16. SCOPE™ Logic Products, Application and data manual, Texas Instruments Inc., 1998.