Automatic test pattern generation for improving the fault coverage of microprocessors

Proceedings of the Asian Test Symposium

Volumn , Issue , 1999, Pages 13-19

  Hirase, Junichi ^a   Yoshimura, Shinichi ^a   Sezaki, Tomohisa ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION (ATPG); FAULT COVERAGE;

AUTOMATIC TESTING; COMPUTER SOFTWARE; DESIGN FOR TESTABILITY;

MICROPROCESSOR CHIPS;

EID: 0033349283     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (5)

1. M. Ixvitt,et.al."Testability, Debuggability, and Manufacturability Feofithas Ultra SPARC-I Micro-processor Prpc IEEE Internati Test)Conf.,pp157- 166, Oct 1995.
2. P.C. Maxwell, R.C Aitken, V Johnso& I.Chang," The Effect of Diffe Testt Sets on Quality Level Prediction When 80% better the 90% Proc. " IEEE International Test Conf., pp 358-364, Oc ti 991.
3. J.Hirase," Improvement of the defect level of m icrocom pul^f testin", Proc. IEEE International Test Con f., pp 377-383, Oct. 1995.
4. M. Athans. R.P. Wishner.&Bertolini, "Suboptimal State estimation for Continuous Time Nonlinear Systems from Discrete Noisy Measurement pp 364-382, 1968.
5. MiròAbramovici, M elvin A. Breuer, Arthur D. Ffiedman, "DIGITAL SYSTEMS TESTING AND TESTABLE DESIGN IEEE PRES pp, 168, 1995.