-
1
-
-
79953830059
-
A taxonomy of accelerator architectures and their programming models. IBM
-
Cascaval, C., Chatterjee, S., Franke, H., Gildea, K., Pattnaik, P.: A taxonomy of accelerator architectures and their programming models. IBM J. Res. Dev. 54(5), 473–482 (2010)
-
(2010)
J. Res. Dev
, vol.54
, Issue.5
, pp. 473-482
-
-
Cascaval, C.1
Chatterjee, S.2
Franke, H.3
Gildea, K.4
Pattnaik, P.5
-
2
-
-
84897749415
-
Disengaged scheduling for fair, protected access to fast computational accelerators
-
ACM
-
Menychtas, K., Shen, K., Scott, M. L.: Disengaged scheduling for fair, protected access to fast computational accelerators. In: Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2014), pp. 301–316. ACM (2014)
-
(2014)
Proceedings of the 19Th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2014)
, pp. 301-316
-
-
Menychtas, K.1
Shen, K.2
Scott, M.L.3
-
4
-
-
84988235942
-
-
Vallina, F. M., Kohn, C., Joshi, P.: Zynq all programmable soc sobel filter implementation using the vivado hls tool, vol. XAPP890, pp. 1–16 (2012)
-
(2012)
Zynq All Programmable Soc Sobel Filter Implementation Using the Vivado Hls Tool
, vol.XAPP890
, pp. 1-16
-
-
Vallina, F.M.1
Kohn, C.2
Joshi, P.3
-
5
-
-
84962921765
-
Optimizing fpga-based accelerator design for deep convolutional neural networks
-
Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., Cong, J.: Optimizing fpga-based accelerator design for deep convolutional neural networks. In: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 161–170. ACM (2015)
-
(2015)
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
, pp. 161-170
-
-
Zhang, C.1
Li, P.2
Sun, G.3
Guan, Y.4
Xiao, B.5
Cong, J.6
-
6
-
-
84908529622
-
A 240 g-ops/s mobile coprocessor for deep neural networks
-
Gokhale, V., Jin, J., Dundar, A., Martini, B., Culurciello, E.: A 240 g-ops/s mobile coprocessor for deep neural networks. In: 2014 IEEE Conference on Computer Vision and Pattern Recognition Workshops (CVPRW), pp. 696–701 (2014)
-
(2014)
2014 IEEE Conference on Computer Vision and Pattern Recognition Workshops (CVPRW)
, pp. 696-701
-
-
Gokhale, V.1
Jin, J.2
Dundar, A.3
Martini, B.4
Culurciello, E.5
-
7
-
-
84913580146
-
Caffe: Convolutional architecture for fast feature embedding
-
ACM
-
Jia, Y., Shelhamer, E., Donahue, J., Karayev, S., Long, J., Girshick, R., Guadarrama, S., Darrell, T.: Caffe: convolutional architecture for fast feature embedding. In: Proceedings of the ACM International Conference on Multimedia, pp. 675–678. ACM (2014)
-
(2014)
Proceedings of the ACM International Conference on Multimedia
, pp. 675-678
-
-
Jia, Y.1
Shelhamer, E.2
Donahue, J.3
Karayev, S.4
Long, J.5
Girshick, R.6
Guadarrama, S.7
Darrell, T.8
-
8
-
-
0004287409
-
-
O’Reilly Media Inc., Sebastopol
-
Corbet, J., Rubini, A., Kroah-Hartman, G.: Linux Device Drivers. O’Reilly Media Inc., Sebastopol (2005)
-
(2005)
Linux Device Drivers
-
-
Corbet, J.1
Rubini, A.2
Kroah-Hartman, G.3
-
9
-
-
84885922370
-
Energy and performance exploration of accelerator coherency port using xilinx zynq
-
ACM
-
Sadri, M., Weis, C., Wehn, N., Benini, L.: Energy and performance exploration of accelerator coherency port using xilinx zynq. In: Proceedings of the 10th FPGAworld Conference, p. 5. ACM (2013)
-
(2013)
Proceedings of the 10Th Fpgaworld Conference
, pp. 5
-
-
Sadri, M.1
Weis, C.2
Wehn, N.3
Benini, L.4
-
10
-
-
84959418007
-
-
Zynq-7000 All Programmable SoC Technical Reference Manual (UG585), Xilinx. Inc., March
-
Zynq-7000 All Programmable SoC Technical Reference Manual (UG585), Xilinx. Inc., March 2013
-
(2013)
-
-
-
11
-
-
70450060046
-
Cnp: An fpga-based processor for convolutional networks
-
IEEE
-
Farabet, C., Poulet, C., Han, J. Y., LeCun, Y.: Cnp: an fpga-based processor for convolutional networks. In: International Conference on Field Programmable Logic and Applications, FPL 2009, pp. 32–37. IEEE (2009)
-
(2009)
International Conference on Field Programmable Logic and Applications, FPL 2009
, pp. 32-37
-
-
Farabet, C.1
Poulet, C.2
Han, J.Y.3
Lecun, Y.4
-
12
-
-
71049121470
-
A massively parallel coprocessor for convolutional neural networks
-
IEEE
-
Sankaradas, M., Jakkula, V., Cadambi, S., Chakradhar, S., Durdanovic, I., Cosatto, E., Graf, H. P.: A massively parallel coprocessor for convolutional neural networks. In: 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2009, pp. 53–60. IEEE (2009)
-
(2009)
20Th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009
, pp. 53-60
-
-
Sankaradas, M.1
Jakkula, V.2
Cadambi, S.3
Chakradhar, S.4
Durdanovic, I.5
Cosatto, E.6
Graf, H.P.7
-
13
-
-
84876231242
-
Imagenet classification with deep convolutional neural networks
-
Krizhevsky, A., Sutskever, I., Hinton, G. E.: Imagenet classification with deep convolutional neural networks. In: Advances in Neural Information Processing Systems, pp. 1097–1105 (2012)
-
(2012)
Advances in Neural Information Processing Systems
, pp. 1097-1105
-
-
Krizhevsky, A.1
Sutskever, I.2
Hinton, G.E.3
-
14
-
-
84959418008
-
-
PetaLinux Tools User Guide, Xilinx. Inc., June
-
PetaLinux Tools User Guide: Board Bringup Guide (UG980), Xilinx. Inc., June 2014
-
(2014)
Board Bringup Guide (UG980)
-
-
-
15
-
-
84959418009
-
-
Amd heterogeneous uniform memory access
-
Rogers, P., Fellow, C.: Amd heterogeneous uniform memory access (2013)
-
(2013)
-
-
Rogers, P.1
Fellow, C.2
-
17
-
-
67650507097
-
Maintaining I/O data coherence in embedded multicore systems
-
Berg, T.: Maintaining I/O data coherence in embedded multicore systems. IEEE Micro 29(3), 10–19 (2009)
-
(2009)
IEEE Micro
, vol.29
, Issue.3
, pp. 10-19
-
-
Berg, T.1
-
18
-
-
84865547094
-
Big. Little processing with arm cortex-a15 & cortex-a7
-
Greenhalgh, P.: Big. little processing with arm cortex-a15 & cortex-a7. ARMWhite paper (2011)
-
(2011)
Armwhite Paper
-
-
Greenhalgh, P.1
-
19
-
-
84864276428
-
Efficient memory allocations on a many-core accelerator
-
IEEE
-
Koutras, I., Bartzas, A., Soudris, D.: Efficient memory allocations on a many-core accelerator. In: ARCS Workshops (ARCS), pp. 1–6. IEEE (2012)
-
(2012)
ARCS Workshops (ARCS)
, pp. 1-6
-
-
Koutras, I.1
Bartzas, A.2
Soudris, D.3
|