A taxonomy of accelerator architectures and their programming models

IBM Journal of Research and Development

Volumn 54, Issue 5, 2010, Pages

  Cascaval, C ^a   Chatterjee, S ^b   Franke, H ^c   Gildea, K J ^b   Pattnaik, P ^c  

^a Qualcomm Research Center   (United States)

^b IBM   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATOR ARCHITECTURES; APPLICATION PERFORMANCE; ARCHITECTURE COMMUNITY; CLOCK FREQUENCY; CURRENT PROCESSORS; DESIGN TRADEOFF; FUNCTIONAL UNITS; HARDWARE DESIGNERS; HARDWARE SYSTEM; HETEROGENEOUS ARCHITECTURES; HETEROGENEOUS PLATFORMS; HIGH FREQUENCY; MULTI CORE; MULTI-CORE SYSTEMS; PORTING SOFTWARE; POWER EFFICIENCY; PROGRAMMING MODELS; RESEARCH EFFORTS; SILICON CHIP; SOFTWARE STACKS; SUPERSCALAR PROCESSOR;

ACCELERATION; COMPUTER HARDWARE; DESIGN; MULTICORE PROGRAMMING; PARALLEL PROCESSING SYSTEMS; TAXONOMIES;

COMPUTER ARCHITECTURE;

EID: 79953830059     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/JRD.2010.2059721     Document Type: Article

References (39)

1. P. Gelsinger, BMicroprocessors for the new millennium: Challenges, opportunities, and new frontiers,[ in Proc. Int. Solid State Circuits Conf., 2001, pp. 22-25. (Pubitemid 32327456)
2. AMD Multicore, Advanced Micro Devices, Sunnyvale, CA, 2009. [Online]. Available: http://www.amd.com/us/ products/technologies/multi-core-processing/ Pages/ multi-core-processing.aspx
3. AMD HyperTransport Technology, Advanced Micro Devices, Sunnyvale, CA, 2009. [Online]. Available: http://www.amd.com/ us/products/technologies/ hypertransport-technology/Pages/hypertransport-technology.aspx
4. ARM Cortex-A9 MP Core, ARM, Cambridge, U.K., 2009. [Online]. Available: http://arm.com/products/CPUs/ ARMCortex-A9-MPCore.html
5. IBM POWER4 System. IBM J. Res. & Dev., vol. 46, no. 1, 2002, entire issue. [Online]. Available: http://ieeexplore.ieee.org/xpl/ tocresult.jsp? isnumber=5389038
6. POWER5 and Packaging. IBM J. Res. & Dev., vol. 49, no. 4/5, 2005, entire issue. [Online]. Available: http://ieeexplore.ieee.org/xpl/tocresult.jsp? isnumber=5388808
7. IBM POWER6 Microprocessor Technology. IBM J. Res. & Dev., vol. 51, no. 6, 2007, entire issue. [Online]. Available: http:// ieeexplore.ieee.org/xpl/ tocresult.jsp?isnumber=5388622
8. Intel Multicore Technology, Intel Corporation, Santa Clara, CA, 2009. [Online]. Available: http://www.intel.com/multi-core/
9. Sun Niagara Processors, 2009. [Online]. Available: http://www. sun.com/processors/niagara
10. M. D. Hill and M. R. Marty, BAmdahl's law in the multicore era,[ Computer, vol. 41, no. 7, pp. 33-38, Jul. 2008.
11. S. Palacharla, N. Jouppi, and J. E. Smith, BComplexity-effective superscalar processors,[ in Proc. ISCA, 1997, pp. 206-218.
12. G. Pfister, Why accelerators now? Jul. 2009. [Online]. Available: http://perilsofparallel.blogspot.com/2009/07/ why-accelerators-now.html
13. Intel Math Co-Processors. [Online]. Available: http://www. cpu-info.com/index2.php?mainid=Copro
14. IBM WebSphere DataPower XML Accelerator, IBM Corporation, Armonk, NY, 2009. [Online]. Available: http://www-01.ibm.com/ software/integration/ datapower/xa35
15. Azul Syst., Mountain View, CA, 2009. [Online]. Available: http:// www.azulsystems.com/
16. A. Hagiescu, W.-F. Wong, D. Bacon, and R. Rabbah, BA computing origami: Folding streams in FPGAs,[ in Proc. 46th DAC, San Francisco, CA, Jul. 2009, pp. 282-287.
17. S. Hauck and A. Dehon, Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation (Systems on Silicon). San Mateo, CA: Morgan Kaufmann, 2007.
18. H. Ziegler and M. Hall, BEvaluating heuristics in automatically mapping multi-loop applications to FPGAs,[ in Proc. ACM/ SIGDA 13th Int. Symp. FPGA, 2005, pp. 184-195. (Pubitemid 40787608)
19. Xilinx Embedded PowerPC Solution, 2005. [Online]. Available: http://www.xilinx.com/prs-rls/ip/0571ppc2mship.htm
20. OpenSparc, 2010. [Online]. Available: http://www.opensparc.net/
21. Intel IXP2800 Network Processor, Intel Corporation, Santa Clara, CA. [Online]. Available: http://download.intel.com/design/ network/ProdBrf/27905403. pdf
22. J. Owens, BGPU architecture overview,[ in Proc. ACM SIGGRAPH Courses, 2007, p. 2.
23. Enabling Ultra Low-Latency Trading, 2009. [Online]. Available: http://www.celoxica.com/
24. H. Franke, J. Xenidis, C. Basso, B. M. Bass, S. S. Woodward, J. D. Brown, and C. L. Johnson, BIntroduction to the wire-speed processor and architecture,[ IBM J. Res. & Dev., vol. 54, no. 1, pp. 3:1-3:11, Jan./Feb. 2010.
25. J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy, BIntroduction to the Cell multiprocessor,[ IBM J. Res. & Dev., vol. 49, no. 4/5, pp. 589-604, Jul. 2005.
26. The Open System Interconnection Model, ISO/IEC Standard 7498, 1994. [Online]. Available: http://standards.iso.org/ittf/ PubliclyAvailableStandards/ s020269-ISO-IEC-7498-1-1994(E).zip.
27. H. Zimmermann, BOSI reference model: The ISO model of architecture for open systems interconnection,[ IEEE Trans. Commun., vol. COM-28, no. 4, pp. 425-432, Apr. 1980.
28. J. C. Mogul, BTCP offload is a dumb idea whose time has come,[ in Proc. HotOS IX, May 2003, pp. 25-30.
29. BLAS: Basic Linear Algebra Subprograms. [Online]. Available: http://www.netlib.org/blas/
30. M. Frigo and S. G. Johnson, BThe design and implementation of FFTW3,[ Proc. IEEEVSpecial Issue FProgram Generation, Optimization, and Platform Adaptation, vol. 93, no. 2, pp. 216-231, Feb. 2005.
31. ICU: International Components for Unicode, 2009. [Online]. Available: http://site.icu-project.org/
32. OpenSSL: Cryptography and SSL/TLS Toolkit. [Online]. Available: http://www.openssl.org/
33. Intel QuickAssist Technology Accelerator Abstraction Layer. [Online]. Available: http://developer.intel.com/technology/ platforms/quickassist/index. htm
34. OpenCL, 2009. [Online]. Available: http://www.khronos.org/ opencl/
35. I. Buck, T. Foley, D. R. Horn, J. Sugerman, K. Fatahalian, M. Houston, and P. Hanrahan, BBrook for GPUs: Stream computing on graphics hardware,[ ACM Trans. Graph., vol. 23, no. 3, pp. 777-786, Aug. 2004.
36. W. R. Mark, R. S. Glanville, K. Akeley, and M. J. Kilgard, BCg: A system for programming graphics hardware in a C-like language,[ in Proc. Int. Conf. Comput. Graph. Interactive Tech., 2003, pp. 896-907.
37. A. Das, W. J. Dally, and P. Mattson, BCompiling for stream processing,[ in Proc. 15th PACT, 2006, pp. 33-42.
38. A. E. Eichenberger, P. Wu, and K. O'Brien, BVectorization for SIMD architectures with alignment constraints,[ in Proc. PLDI, 2004, pp. 82-93.
39. D. Nuzman, I. Rosen, and A. Zaks, BAuto-vectorization of interleaved data for SIMD,[ in Proc. PLDI, 2006, pp. 132-143.