Verification using uninterpreted functions and finite instantiations

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1166, Issue , 1996, Pages 218-232

  Hojati, Ramin ^a   Isles, Adrian ^a   Kirkpatrick, Desmond ^a   Brayton, Robert K ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL METHODS;

ABSTRACT MODELING; CORRECTNESS PROPERTIES; INTEGER VARIABLES; PARTIAL VERIFICATION; REACHABILITY PROBLEM; STATE EXPLOSION PROBLEMS; SUPERSCALAR MICRO-PROCESSORS; UNINTERPRETED FUNCTIONS;

COMPUTER AIDED DESIGN;

EID: 84957627890     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/BFb0031810     Document Type: Conference Paper

References (23)

1. V. Bhagwati, S. Devadas, "Automatic Verification of Pipelined Microprocessors", Proceedings of 31st Design Automation Conference, 1994.
2. J. Burch, "Techniques for Verifying Superscalar Microprocessors", Design Automation Conference, 1996.
3. J. Burch, D. Dill, "Automated Verification of Pipelined Micro-processors", Computer-Aided Verification, 1994.
4. Ed C. Clarke, X. Zhao, "Word Level Model Checking, A New Approach for Verifying Arithmetic Orcuits", Technical Report, Carnegie Melon University, May 1995.
5. Szu-Tsung Cheng and Robert K Brayton, "Compiling Verilog into Automata", University of California at Berkeley", Memorandum UCB/ERL M94137, 1994.
6. F. Corella, "Automatic High-Level Verification Against Clocked Algorithmic Specifications", Proceedings of the IFIP WG10.2 Conference on Computer Hardware Description Languages and their Applications, Ottawa, Canada, Apr. 1993. Elsevier Science Publishers B.V.
7. David Cyrluk, "Microprocessor Verification in PVS: A Methodology and Simple Example", Technical Report SRI-CSL-93-12, Computer Science Laboratory, SRI International, December 1993.
8. D- Cyrluk, P. Narendran, "Ground Temporal Logic: A Logic for Hardware Verification", Computer- Aided Verification, 1994.
9. D. Cyrluk, private communication, 1995.
10. John L. Hennessy, David A. Patterson, "Computer Architecture A Quantitative Approach", Morgan Kaufmann Publishers, 1990.
11. Richard C. Ho, Han Yang, Mark A. Horowitz, David L. Dill, "Architecture Validation for Processors", Proceedings of the 22nd Annual Int. Symposium on Computer Architecture, June 1995.
12. R. Hojati, R. K. Brayton, "Automatic Datapath Abstraction of Hardware Systems", Conference on Computer-Aided Verification, 1995.
13. R. Hojati, R. Mueller-Thnns, P. Loewenstein, R. K. Brayton, "Automatic Verification of Memory Systems which Execute Their Instructions Out of Order", Conference on Hardware Description Languages and Their Applications, 1995.
14. A. Aziz, F. Balarin, S. T. Cheng, R. Hojati, T. Kam, S. C. Krishnan, R. K. Ranjan, T. R. Shiple, V. Singhal, S. Tasiran, H.-Y. Wang, R. K. Braytan and A. L. Sangiovanni-Vincentelli, "HSIS: A BDD Based Environment for Formal Verification ", Design Automation Conference, 1994.
15. Peter Yan-Tek Hsu, "Design of the R8000 Microprocessor", IEEE Micro 1993. Also available at http://www.mips.com under R8000 microprocessor.
16. John E. Hopcroft, Jeffery D. Ullman, "Introduction to Automata Theory, Languages, and Computation", Addison-Wesley, 1979.
17. Mike Johnson, "Superscalar Microprocessor Design", Prentice Hall, 1991.
18. D.C. Luckham, D.M.R. Park, and M.S. Patterson, ' On Formahzed Computer Programs, Journal of Computer and System Sciences, 4, 3, pp. 220-249, June 1970.
19. A. Charnas, et al. "A 64b Microprocessor with Multimedia Support", International Solid-State Circuits Conference, pp178-179, Feb, 1995.
20. C.H. Seger, R. E. Bryant, "Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories", Formal Methods in System Design, 6:147-189, 1995.
21. Toru Shonai, Tsuguo Shimiza, "Formal Verification of Pipelined and Superscalar Processors", Conference on Hardware Description Languages, Tokyo, Japan, August 1995.
22. James E. Smith and Andrew R. Pleszkun, "Implementing Precise Interrupts in Pipelined Processors", IEEE Transactions on Computers, Vol. 37, No. 5, May 1986.
23. Mandayam K. Srivas, Steven P. Miller "Applying Formal-verfication to a Commercial Micro- processor", Conference on Hardware Description Languages, Tokyo, Japan, August 1995.