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Volumn 2102, Issue , 2001, Pages 104-117

Transformation-based verification using generalized retiming

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTER SCIENCE; COMPUTERS;

EID: 84958742074     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44585-4_10     Document Type: Conference Paper
Times cited : (16)

References (16)
  • 3
    • 0027072656 scopus 로고
    • HITEC: A test generation package for sequential circuits
    • IEEE, February
    • T. Niermann and J. H. Patel, “HITEC: A test generation package for sequential circuits,” in The European Conference on Design Automation, pp. 214–218, IEEE, February 1991.
    • (1991) The European Conference on Design Automation , pp. 214-218
    • Niermann, T.1    Patel, J.H.2
  • 4
    • 33746763910 scopus 로고
    • Retiming synchronous circuitry
    • C. Leiserson and J. Saxe, “Retiming synchronous circuitry,” Algorithmica, vol. 6, pp. 5–35, 1991.
    • (1991) Algorithmica , vol.6 , pp. 5-35
    • Leiserson, C.1    Saxe, J.2
  • 16
    • 84957376851 scopus 로고    scopus 로고
    • VIS: A system for verification and synthesis
    • The VIS Group, Springer-Verlag, July
    • The VIS Group, “VIS: A system for verification and synthesis,” in Conference on Computer Aided Verification (CAV’96), pp. 428–432, Springer-Verlag, July 1996.
    • (1996) Conference on Computer Aided Verification (CAV’96) , pp. 428-432


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.