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Volumn 1703, Issue , 1999, Pages 350-355

Exploiting retiming in a guided simulation based validation methodology

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EID: 84958633682     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-48153-2_32     Document Type: Conference Paper
Times cited : (2)

References (8)
  • 2
    • 84958605014 scopus 로고    scopus 로고
    • Digital computer technology and design: Fall 1994 project
    • P. Franzon. Digital computer technology and design: Fall 1994 project. Private Communication, 1996.
    • (1996) Private Communication
    • Franzon, P.1
  • 3
    • 0030679993 scopus 로고    scopus 로고
    • Toward formalizing a validation methodology using simulation coverage
    • June
    • A. Gupta, S. Malik, and P. Ashar. Toward formalizing a validation methodology using simulation coverage. In Proc. 34th Design Automation Conf., pages 740–745, June 1997.
    • (1997) Proc. 34Th Design Automation Conf , pp. 740-745
    • Gupta, A.1    Malik, S.2    Ashar, P.3
  • 7
    • 33746763910 scopus 로고
    • Retiming Synchronous Circuitry
    • Charles E. Leiserson and James B. Saxe. Retiming Synchronous Circuitry. Algorithmica, 6(1):5–36, 1991.
    • (1991) Algorithmica , vol.6 , Issue.1 , pp. 5-36
    • Leiserson, C.E.1    Saxe, J.B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.