A novel framework for logic verification in a synthesis environment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 1, 1996, Pages 20-37

  Kunz, Wolfgang ^a   Pradhan, Dhiraj K ^a   Reddy, Subodh M ^a  

^a LEIBNIZ UNIVERSITY HANNOVER   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE DESCRIPTION LANGUAGES; ELECTRIC NETWORK SYNTHESIS; EQUIVALENT CIRCUITS; FORMAL LOGIC; LEARNING SYSTEMS; RECURSIVE FUNCTIONS;

FORMAL LOGIC VERIFICATION; FUNCTIONAL METHODS; LOGIC NETWORK; RECURSIVE LEARNING; STRUCTURAL PREPROCESSING; SYNTHESIS ENVIRONMENT;

COMPUTER AIDED LOGIC DESIGN;

EID: 0029756570     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.486269     Document Type: Article

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