Device design guideline for steep slope ferroelectric FET using negative capacitance in sub-0.2V operation: Operation speed, material requirement and energy efficiency

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2015-August, Issue , 2015, Pages T212-T213

  Kobayashi, Masaharu ^a   Hiramoto, Toshiro ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

FeFET; ferroelectric; Negative capacitance

Indexed keywords

CAPACITANCE; DESIGN; FERROELECTRIC MATERIALS; FERROELECTRICITY;

FEFET; FERROELECTRIC POLARIZATION; HYSTERESIS FREE; LOW SUPPLY VOLTAGES; MATERIAL REQUIREMENTS; NEGATIVE CAPACITANCE; OPERATION SPEED; OPTIMIZED DEVICES;

ENERGY EFFICIENCY;

EID: 84951084500     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2015.7223678     Document Type: Conference Paper

References (10)

1. H. Fuketa et al., IEDM 2011 p. 559
2. S. Salahuddin and S. Datta, IEDM 2008 p. 693
3. A. Khan et al., IEDM 2011 p. 255
4. M. H. Park et al., APL 102 242905 (2013)
5. M. H. Park et al., APL 105 072902 (2014)
6. S. Mueller et al., Adv. Funct. Mater. 22 2412 (2012)
7. J. Muller et al., Nano Lett. 12 4318 (2012)
8. T. S. Boscke et al., APL 99 102903 (2011)
9. T. S. Boscke et al., IEDM 2011 p. 547
10. T. Shimizu et al., JJAP 53 09PA04 (2014)