GRIP: A reconfigurable architecture for host-based gigabit-rate packet processing

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2002-January, Issue , 2002, Pages 121-130

  Bellows, Peter ^a   Flidr, Jarostov ^a   Lehman, Tom ^a   Schott, Brian ^a   Underwood, Keith D ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; ETHERNET; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTERFACES (COMPUTER); NETWORK ARCHITECTURE; NETWORK LAYERS; PACKET NETWORKS; RECONFIGURABLE ARCHITECTURES; TELECOMMUNICATION NETWORKS;

ACHIEVABLE THROUGHPUTS; APPLICATION LAYERS; GIGABIT ETHERNET; HIGH PERFORMANCE NETWORKS; NETWORK PROCESSING; PACKET PROCESSING; PROCESSING CAPABILITY; SECOND-GENERATION DESIGN;

COMPUTER ARCHITECTURE;

EID: 84950126590     PISSN: 10823409     EISSN: None     Source Type: Journal    
DOI: 10.1109/FPGA.2002.1106667     Document Type: Article

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