A bit-serial implementation of the International Data Encryption Algorithm IDEA

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2000-January, Issue , 2000, Pages 122-131

  Leong, M P ^a   Cheung, O Y H ^a   Tsoi, K H ^a   Leong, P H W ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; CRYPTOGRAPHY; HIGH SPEED NETWORKS; NETWORK ARCHITECTURE;

AND INTERNATIONAL DATA ENCRYPTION ALGORITHMS (IDEA); BIT SERIAL IMPLEMENTATION; BIT-SERIAL ARCHITECTURE; HIGH PERFORMANCE IMPLEMENTATIONS; INTERNATIONAL DATA ENCRYPTION ALGORITHMS; SOFTWARE IMPLEMENTATION; SYSTEM CLOCK RATES; THREE ORDERS OF MAGNITUDE;

ALGORITHMS;

EID: 84948707708     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2000.903399     Document Type: Conference Paper

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