Acceleration of a 2D-FFT on an Adaptable Computing Cluster

Proceedings - 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001

Volumn , Issue , 2001, Pages 180-189

  Underwood, K D ^a   Sass, R R ^a   Ligon, W B ^a  

^a Clemson University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; FAST FOURIER TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE HARDWARE;

2D FAST FOURIER TRANSFORMS; CLUSTER-BASED; COMPUTING APPLICATIONS; COMPUTING CLUSTERS; CUSTOM COMPUTING MACHINES; NETWORK FUNCTIONALITY; PERFORMANCE AND SCALABILITIES; TARGET APPLICATION;

CLUSTER COMPUTING;

EID: 84963963442     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. M. Blumrich, K. Li, R. Alpert, C. Dubnicki, and E. Felten. Virtual memory mapped network interface for the SHRIMP multicomputer. In 21st Annual International Symposium on Computer Architecture, pages 142-153, Chicago, Illinois, USA, Apr. 1994.
2. N. J. Boden, D. Cohen, R. E. F. A. E. Kulawik, C. L. Seitz, J. N. Seizovic, and W.-K. Su. Myrinet: A gigabit-per-second local area network. IEEE Micro, 15(1), Feb. 1995.
3. P. Buonadonna, A. Geweke, and D. E. Culler. Implementation and analysis of the virtual interface architecture. In Proceedings of the 1998 conference on Supercomputing, Nov. 1998.
4. Y. Coady, J. S. Ong, and M. J. Feeley. Using embedded network processors to implement global memory management in a workstation cluster. In Proceedings of The Eighth IEEE International Symposium on High Performance Distributed Computing, Redondo Beach, California, USA, Aug. 1999.
5. D. E. Culler, A. Arpaci-Dusseau, R. Arpaci-Dusseau, B. Chun, S. Lumetta, A. Mainwaring, R. Martin, C. Yoshikawa, and F. Wong. Parallel computing on the Berkeley NOW. In 9th Joint Symposium on Parallel Processing, Kobe, Japan, 1997.
6. A. Dandalis, V. K. Prasanna, and J. D. P. Rolim. An adaptive cryptographic engine for IPSec architectures. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 132-141, Napa Valley, CA, April 2000.
7. B. Falsafi and D. A. Wood. Scheduling communication on an SMP node parallel machine. In Proceedings of Third International Symposium on High Performance Computer Architecture, San Antonio, Texas, USA, Feb. 1997.
8. M. E. Fiuczynski, R. P. Martin, T. Owa, and B. N. Bershad. SPINE: A safe programmble and integrated network environment. In Eighth ACM SIGOPS European Workshop, Sept. 1998.
9. M. Frigo and S. G. Johnson. FFTW: An adaptive software architecture for the FFT. In Proceedings of International Conference on Acoustics, Speech and Signal Processing, volume 3, pages 1381-1384, Seattle, WA, May 1998.
10. J. R. Hess, D. C. Lee, S. J. Harper, M. T. Jones, and P. M. Athanas. Implementation and evaluation of prototype reconfigurable router. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 44-50, Napa Valley, CA, April 1999.
11. M. Jones, L. Scharf, J. Scott, C. Twaddle, M. Yaconis, K. Yao, and P. Athanas. Implementing an API for distributed adaptive computing systems. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 222-230, Napa Valley, CA, April 1999.
12. J. W. Lockwood, J. S. Turner, and D. E. Taylor. Field programmable port extender (FPX) for distributed routing and queueing. In Proceedings of the ACM International Symposium on Field Programmable Gate Arrays, pages 30-39, Napa Valley, CA, April 1997.
13. J. T. McHenry, P. W. Dowd, F. A. Pellegrino, T. M. Carrozzi, and W. B. Cocks. An FPGA-based coprocessor for ATM firewalls. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pages 30-39, Napa Valley, CA, April 1997.
14. L. Moll, A. Heirich, and M. Shand. Sepia: scalable 3d compositing using PCI Pammette. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 146-155, Napa Valley, CA, April 1999.
15. T. Mummert, C. Kosak, P. Steenkiste, and A. Fisher. Fine grain parallel communication on general purpose LANs. In In Proceedings of 1996 International Conference on Super-computing (ICS96), pages 341-349, Philadelphia, PA, USA, May 1996.
16. S. K. Reinhardt, J. R. Larus, and D. A. Wood. Tempest and typhoon: User-level shared memory. In International Conference on Computer Architecture, pages 260-267, Chicago, Illinois, USA, Apr. 1994.
17. M.-C. Ros¸u, K. Schwan, and R. Fujimoto. Supporting parallel applications on clusters of workstations: The intelligent network interface approach. In Proceeding of the 6th International Symposium on High Performance Distributed Computing (HPDC 97), 1997.
18. S. Sumimoto, H. Tezuka, A. Hori, H. Harada, T. Takahashi, and Y. Ishikawa. The design and evaluation of high performance communication using a Gigabit Ethernet. In International Conference on Supercomputing, pages 260-267, Rhodes, Greece, June 1999.
19. T. von Eicken, A. Basu, V. Buch, and W. Vogels. U-net: a user-level network interface for parallel and distributed computing. In Proceedings of the 15th ACM Symposium on Operating Systems Principles (SOSP), pages 40-53, Dec. 1995.
20. T. von Eicken, D. E. Culler, S. C. Goldstein, and K. E. Schauser. Active messages: a mechanism for integrated communication and computation. In Proceedings of the 19th annual international symposium on Computer architecture, pages 256-266, May 1992.
21. C.-C. Yeh, C.-H. Wu, and J.-Y. Juang. Design and implementation of a multicomputer interconnection network using FPGAs. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pages 30-39, Napa Valley, CA, April 1995.