High performance DES Encryption in virtex™ FPGAs using JBits™

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2000-January, Issue , 2000, Pages 113-121

  Patterson, Cameron ^a  

^a XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION PROGRAMMING INTERFACES (API); BINARY SEQUENCES; COMPUTATION THEORY; COMPUTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); JAVA PROGRAMMING LANGUAGE;

BIT STREAM; CONFIGURATION BITSTREAM; CRYPTOGRAPHIC KEY; DATA ENCRYPTION STANDARD; DYNAMIC CIRCUITS; GIGABITS PER SECOND; JAVA-BASED APPLICATIONS; PRIMITIVE OPERATIONS;

CRYPTOGRAPHY;

EID: 84949773835     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2000.903398     Document Type: Conference Paper

References (24)

1. http://www.nist.gov/aes.
2. http://www.xilinx.com/products/virtex.htm.
3. http://www.cast-inc.com/cores/xdes.
4. S. Charlwood and P. James-Roxby. Evaluation of the XC6200-series architecture for cryptographic applications. In R. W. Hartenstein and A. Keevallik, editors, Eighth International Workshop on Field-Programmable Logic and Applications (FPL'98), pages 218-227. Springer-Verlag Lecture Notes in Computer Science, Volume 1482, Aug. 1998.
5. http://www.free-ip. com/DES/index.htm.
6. S. Guccione, D. Levi, and R Sundararajan. JBits: Java based interface for reconfigurable computing. In Second Annual Military and Aerospace Applications of Programmable Devices and Technologies (MAPLD'99), The Johns Hopkins University, Laurel, Maryland, Sep. 1999.
7. J.-R Kaps. High speed FPGA architectures for the Data Encryption Standard. Master's thesis, Department of Electrical Engineering, Worcester Polytechnic Institute, May 1998.
8. T. Kean and A. Duncan. DES key breaking, encryption and decryption on the XC6216. In K. L. Pocek and J. M. Arnold, editors, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'98), pages 310-311, Apr. 1998.
9. S. Kelem. Virtex Configuration Architecture Advanced User's Guide. Xilinx, Inc., 2100 Logic Drive, San Jose, California, Jun. 1999. Application Note 151.
10. E. Keller. JRoute: a run-time routing API for FPGA hardware. In Seventh Reconfigurable Architectures Workshop (RAW 2000), Cancun, Mexico, May 2000.
11. J. Leonard and W. H. Mangione-Smith. A case study of partially evaluated hardware circuits: Key-specific DES. In W. Luk, P. Y. Cheung, and M. Glesner, editors, Seventh International Workshop on Field-Programmable Logic and Applications (FPL'97), pages 151-160. Springer-Verlag Lecture Notes in Computer Science, Volume 1304, Sep. 1997.
12. http://www.memecdesign. com/product.
13. N. B. of Standards. FIPS PUB 46, The Data Encryption Standard. U. S. Department of Commerce, Jan 1977.
14. N. I. of Standards and Technology. Announcing request for candidate algorithm nominations for the Advanced Encryption Standard (AES). Federal Register, 62(117):48051-48058, Sep. 1997.
15. B. Schneier. Applied Cryptography. John Wiley & Sons, Inc., second edition, 1996.
16. B. Schneier, J. Kelsey, D. Whiting, D. Wagner, C. Hall, and N. Ferguson. The Twofish Encryption Algorithm. John Wiley & Sons, Inc., 1999.
17. http://www.cl.cam.ac.uk/~rjal4/serpent.html.
18. R. R. Taylor and S. C. Goldstein. A high-performance flexible architecture for cryptography. In C etin K. Koc and C. Paar, editors, First International Workshop on Cryptographic Hardware and Embedded Systems (CHES'99), pages 231-245. Springer-Verlag Lecture Notes in Computer Science, Volume 1717, Aug. 1999.
19. S. Trimberger. High-Speed DES Encryptor/Decryptor. Xilinx, Inc., 2100 Logic Drive, San Jose, California. Application Note, to appear.
20. D. C. Wilcox, L. G. Pierson, P. J. Robertson, E. L. Witzke, and K. Gass. A DES ASIC suitable for network encryption at 10 Gbps and beyond. In Cetin K. Koc and C. Paar, editors, First International Workshop on Cryptographic Hardware and Embedded Systems (CHES'99), pages 37-48. Springer-Verlag Lecture Notes in Computer Science, Volume 1717, Aug. 1999.
21. http://www.xentec-inc.com/indx-products.html.
22. Xilinx, Inc., 2100 Logic Drive, San Jose, California. Virtex 2.5V FPGA Series Data Sheet, Oct. 1999.
23. Xilinx, Inc., 2100 Logic Drive, San Jose, California. Spartan-II 2.5V Family FPGA Data Sheet, Mar. 2000.
24. P. Zimmermann. PGP Source Code and Internals. MIT Press, Boston, 1995.