An assessment of the behavior of compact thermal models of electronic packages in a printed circuit board level environment

InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITHERM

Volumn 2002-January, Issue , 2002, Pages 69-76

  DeVoe, J ^a   Ortega, A ^a  

^a University of Arizona   (United States)

Author keywords

Anisotropic magnetoresistance; Circuit testing; Electronic packaging thermal management; Finite element methods; Performance analysis; Performance evaluation; Predictive models; Printed circuits; Temperature; Thermal conductivity

Indexed keywords

ANISOTROPY; ELECTRIC NETWORK ANALYSIS; ELECTRONICS PACKAGING; ENHANCED MAGNETORESISTANCE; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT TESTING; PRINTED CIRCUITS; TEMPERATURE; THERMAL CONDUCTIVITY; THERMOGRAPHY (TEMPERATURE MEASUREMENT);

CIRCUIT TESTING; ELECTRONIC PACKAGING THERMAL MANAGEMENTS; PERFORMANCE ANALYSIS; PERFORMANCE EVALUATION; PREDICTIVE MODELS;

FINITE ELEMENT METHOD;

EID: 84950123608     PISSN: 19363958     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITHERM.2002.1012440     Document Type: Conference Paper

References (14)

1. C.J.M. Lasance, H. Rosten and J.D. Parry, "The world of thermal characterization according to DELPHI-Parts I and II: experimental and numerical methods", IEEE Trans. Comp., Packaging, Manufact. Technol., Part A, vol. 20, no.4, pp. 392-398, Dec 1997
2. A. Aranyosi, A. Ortega, J. Evans, T. Tarter, J. Pursel, J. Radhakrishnan, "Development of Compact Thermal Models for Advanced Electronic Packaging: Methodology and Experimental Validation for a Single-Chip CPGA Package", IEEE Inter Society Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, pp. 225-232, 2000.
3. W. Wang, S. Liou, Y.S. Sun, "Bridging The Gap: Package Level and System Level Thermal Modelling", Electronic Components & Technology Conference, 2000. 2000 Proceedings. 50th, 2000 Page(s): 287-293
4. V.H. Adams, D.L. Blackburn, Y.K. Joshi, D.W. Berning, "Issues in Validating Package Compact Thermal Models for Natural Convection Cooled Electronic Systems", IEEE Trans. Comp., Packaging, Manufact. Technol., Part A, vol. 20, no. 4, pp. 420-431, Dec 1997.
5. S. Shidore, V. Adams, T. Lee, "A Study of Compact Thermal Model Topologies in CFD for a Flip Chip Plastic Ball Grid Array Package", IEEE Trans. Comp., Packaging, Manufact. Technol, vol. 24, no. 2, pp. 191-198, June 2001.
6. A. Aranyosi, A. Ortega, R.A. Griffin, S. West, D.R. Edwards, "Compact Thermal Models of Packages Used in Conduction Cooled Applications", IEEE Trans. Comp. And Packaging Technol, vol. 23, no.34, pp. 470-480, Sept 2000.
7. J. DeVoe, A. Ortega, "An Investigation of Board Level Effects on Compact Thermal Models of Electronic Chip Packages", in Proc. SEMITHERM-XVIII, San Jose, CA, 2002
8. M. Touzelbaev, Advanced Micro Devices, Sunnyvale, CA, Personal communication, July 2001.
9. B.M. Guenin, Amkor Technology, Inc., Chandler, AZ, Personal communication, Sept 2001.
10. S. Duggan, "JEDEC 'Round Robin' Testing for Industry Correlation and Model Generation", Internal Thermal Test Report TT-01-11, Amkor Technology, Inc., Chandler, AZ
11. th THERMINIC Int. Workshop, Budapest, 2000.
12. EIA/JESD51-9, "Test Boards for Area Array Surface Mount Package Thermal Measurements", Electronics Industries Association, Engineering Department.
13. EIA/JESD51-11, "Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements", Electronics Industries Association, Engineering Department.
14. D. Edwards, "Development of JEDEC Standard Thermal Measurement Test Boards", IEEE Trans. Comp., Packaging, Manufact. Technol., Part A, vol. 19, no. 4, pp. 478-485, Dec 1996.