Multilayer VLSI layout for interconnection networks

Proceedings of the International Conference on Parallel Processing

Volumn 2000-January, Issue , 2000, Pages 33-40

  Yeh, Chi Hsiang ^a   Varvarigos, E A ^b   Parhami, B ^b  

^a QUEEN S UNIVERSITY   (Canada)

^b University of California   (United States)

Author keywords

Concurrent computing; Costs; Distributed computing; Hypercubes; Multiprocessor interconnection networks; Nonhomogeneous media; Parallel processing; Very large scale integration; Wires; Wiring

Indexed keywords

COSTS; ELECTRIC WIRING; GEOMETRY; HYPERCUBE NETWORKS; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING); MULTILAYERS; VLSI CIRCUITS; WIRE;

BUTTERFLY NETWORKS; CONCURRENT COMPUTING; CUBE-CONNECTED CYCLES; GENERALIZED HYPERCUBES; HIERARCHICAL HYPERCUBE; HYPER-CUBES; NONHOMOGENEOUS MEDIA; PARALLEL PROCESSING;

DISTRIBUTED COMPUTER SYSTEMS;

EID: 84949487189     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2000.876069     Document Type: Conference Paper

References (37)

1. Adams, G.B. and H.G. Siegel, "The extra stage cube: a fault-tolerant interconnection network for supersystems," IEEE Trans. Comput., vol. 31, no. 5, May. 1982, pp. 443-454.
2. Akers, S.B. and B. Krishnamurthy, "A group-theoretic model for symmetric interconnection networks," IEEE Trans. Comput., Vol. 38, Apr. 1989, pp. 555-565.
3. Avior, A., T. Calamoneri, S. Even, A. Litman, and A. Rosenberg, "A tight layout of the butterfly network," Theory Comput. Sys., vol. 31, no. 4, 1998, pp. 475-488.
4. Basak, D. and D.K. Panda, "Designing clustered multiprocessor systems under packaging and technological advancements," IEEE Trans. Parallel Distrib. Sys., vol. 7, no. 9, Sep. 1996, pp. 962-978.
5. Bhuyan, L.N. and D.P. Agrawal, "Generalized hypercube and hyperbus structures for a computer network," IEEE Trans. Comput., vol. 33, no. 4, Apr. 1984, pp. 323-333.
6. Brady, M.L. and M. Sarrafzadeh, "Stretching a knock-knee layout for multilayer wiring," IEEE Trans. Computers, vol. 39, no. 1, Jan. 1990, pp. 148-151.
7. Brebner, G., "Relating routing graphs and two-dimensional grids," VLSI: Algorithms and Architectures, 1985, pp. 221-231.
8. Chen, G. and F.C.M. Lau, "Tighter layouts of cube-connected cycles," IEEE Trans. Parallel Distrib. Sys, IEEE Trans. Parallel Distrib. Sys., vol. 11, no. 2, Feb. 2000, pp. 182-191.
9. Dally, W.J. and S. Lacy, "VLSI architecture: past, present, and future," Proc. Advanced Research in VLSI Conf., 1999, pp. 232-241.
10. Dinitz, Y., S. Even, R. Kupershtok, and M. Zapolotsky, "Some compact layouts of the butterfly," Proc. ACM Symp. Parallel Algorithms and Architectures, Jun. 1999, pp. 54-63.
11. Efe, K. and A. Fernandez, "Products of networks with logarithmic diameter and fixed degree," IEEE Trans. Parallel Distrib. Sys., vol. 6, no. 9, Sep. 1995, pp. 963-975.
12. Even, S., S. Muthukrishnan, M.S. Paterson, and S. Cenk Sahinalp, "Layout of the Batcher bitonic sorter," Proc. ACM Symp. Parallel Algorithms and Architectures, 1998, pp. 172-181.
13. Fernández, A. and K. Efe, "Efficient VLSI layouts for homogeneous product networks," IEEE Trans. Computer, vol. 46, no. 10, Oct. 1997, pp. 1070-1082.
14. Lakshmivarahan, S. and S.K. Dhall, "A new hierarchy of hypercube interconnection schemes for parallel computers," J. Supercomputing, vol. 2, 1988, pp. 81-108.
15. Latifi, S., M.M. de Azevedo, and N. Bagherzadeh, "The star connected cycles: a fixed-degree network for parallel processing," Proc. Int'l Conf. Parallel Processing, Vol. I, 1993, pp. 91-95.
16. Latifi, S. and P.K. Srimani, "Transposition networks as a class of fault-tolerant robust networks," IEEE Trans. Parallel Distrib. Sys., Vol. 45, no. 2, Feb. 1996, pp. 230-238.
17. Leighton, F.T., Complexity Issues in VLSI : Optimal Layouts for the Shuffle-exchange Graph and Other Networks Cambridge, Mass., MIT Press, 1983.
18. Leighton, F.T., Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes,Morgan-Kaufman, San Mateo, CA, 1992.
19. Leiserson, C.E., Area-Efficient VLSI Computation, Cambridge, MA, MIT Press, 1983.
20. Leiserson, C.E., "Fat-trees: universal networks for hardware-efficient supercomputing," IEEE Trans. Computers, vol. C-34, no. 10, Oct. 1985, pp. 892-901.
21. Muthukrishnan, S., M.S. Paterson, S. Cenk Sahinalp, and T. Suel, "Compact grid layouts of some multi-level networks," Proc. ACM Symp. Theory of Computing, 1999, to appear.
22. Preparata, F.P. and J.E. Vuillemin, "The cube-connected cycles: a versatile network for parallel computation," Commun. ACM, vol. 24, No. 5, pp. 300-309, May 1981.
23. Thompson, C.D., "Area-time complexity for VLSI," Proc. ACM Symp. Theory of Computing, 1979, pp. 81-88.
24. Thompson, C.D., "A complexity theory for VLSI," Ph.D. dissertation, Dept. of Computer Science, Carnegie-Mellon Univ., Pittsburgh, PA, 1980.
25. Ullman, J.D., Computational Aspects of VLSI, Rockville, MD., Computer Science Press, 1984.
26. Varvarigos, E.A., "Static and dynamic communication in parallel computing," Ph.D. dissertation, Dept. Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 1992.
27. Wise, D.S., "Compact layouts of banyan/FFT networks," VLSI Systems and Computations, Computer Science Press, 1981, pp. 186-195.
28. Yeh, C.-H., "Efficient low-degree interconnection networks for parallel processing: topologies, algorithms, VLSI layouts, and fault tolerance," Ph.D. dissertation, Dept. Electrical & Computer Engineering, Univ. of California, Santa Barbara, Mar. 1998.
29. Yeh, C.-H. and E.A. Varvarigos, "Macro-star networks: efficient low-degree alternatives to star graphs," IEEE Trans. Parallel Distrib. Sys., Vol. 9, no. 10, Oct. 1998, pp. 987-1003.
30. Yeh, C.-H. and B. Parhami, "VLSI layouts of complete graphs and star graphs," Information Processing Letters, Vol. 68, Oct. 1998, pp. 39-45.
31. Yeh, C.-H., E.A. Varvarigos, and B. Parhami, "Efficient VLSI layouts of hypercubic networks," Proc. Symp. Frontiers of Massively Parallel Computation, Feb. 1999, pp. 98-105.
32. Yeh, C.-H., B. Parhami, and E.A. Varvarigos, "The recursive grid layout scheme for VLSI layout of hierarchical networks," Proc. Merged Int'l Parallel Processing Symp. & Symp. Parallel and Distributed Processing, Apr. 1999, pp. 441-445.
33. Yeh, C.-H. and B. Parhami, "The index-permutation graph model for hierarchical interconnection networks," Proc. Int'l Conf. Parallel Processing, Sep. 1999, pp. 48-55.
34. Yeh, C.-H. and B. Parhami, "A unified model for hierarchical networks based on an extension of Cayley graphs," IEEE Trans. Parallel Distrib. Sys., to appear.
35. Yeh, C.-H., B. Parhami, E.A. Varvarigos, and H. Lee, "VLSI layout and packaging of butterfly networks," Proc. ACM Symp. Parallel Algorithms and Architectures, 2000, to appear.
36. Yun S.-K. and K.H. Park, "Hierarchical hypercube networks (HHN) for massively parallel computers," J. Parallel Distrib. Comput., vol. 37, no. 2, Sep. 1996, pp. 194-199.
37. Ziavras, S.G., "RH: a versatile family of reduced hypercube interconnection networks," IEEE Trans. Parallel Distrib. Sys., vol. 5, no. 11, Nov. 1994, pp. 1210-1220.