Designing clustered multiprocessor systems under packaging and technological advancements

IEEE Transactions on Parallel and Distributed Systems

Volumn 7, Issue 9, 1996, Pages 962-978

  Basak, Debashis ^a,b   Panda, Dhabaleswar K ^a,b  

^a IEEE

^b OHIO STATE UNIVERSITY   (United States)

Author keywords

Clustered architectures; Hierarchical organization; Interconnection networks; k ary n cube interconnection; Multiprocessor systems; Packaging constraints; Parallel architectures; Scalable systems

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC NETWORK TOPOLOGY; ELECTRONICS PACKAGING; HIERARCHICAL SYSTEMS; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; PRINTED CIRCUIT BOARDS; SYSTEMS ANALYSIS;

CLUSTERED ARCHITECTURES; PACKAGING CONSTRAINTS; PARALLEL ARCHITECTURE; SCALABLE SYSTEMS;

MULTIPROCESSING SYSTEMS;

EID: 0030244684     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.536940     Document Type: Article

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