A tight layout of the butterfly network

Theory of Computing Systems

Volumn 31, Issue 4, 1998, Pages 475-488

  Avior, A ^a   Calamoneri, T ^b   Even, S ^a   Litman, A ^a   Rosenberg, A L ^c  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^b SAPIENZA UNIVERSITY OF ROME   (Italy)

^c Biologically Inspired Neural and Dynamical Systems Laboratory   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL TECHNIQUES;

BUTTERFLY NETWORKS; LAYOUT AREA; LOW ORDER; LOWER BOUNDS; UPPER AND LOWER BOUNDS; UPPER BOUND;

COMPUTER SCIENCE;

EID: 0032391546     PISSN: 14324350     EISSN: 14330490     Source Type: Journal    
DOI: 10.1007/s002240000098     Document Type: Article

References (17)

1. F. Berman and L. Snyder (1987): On mapping parallel algorithms into parallel architectures. J. Parallel Distrib. Comput. 4, 439-458.
2. S.N. Bhatt, F.R.K. Chung, J.-W. Hong, F.T. Leighton, B. Obrenić, A.L. Rosenberg, and E.J. Schwabe (1996): Optimal emulations by butterfly-like networks. J. Assoc. Comput. Mach. 43, 293-330.
3. S.N. Bhatt and F.T. Leighton (1984): A framework for solving VLSI graph layout problems. J. Comput. System Sci. 28, 300-343.
4. S.H. Bokhari (1981): On the mapping problem. IEEE Trans. Comput. 30, 207-214.
5. R.P. Brent and H.T. Kung (1980): On the area of binary tree layouts. Inform. Process. Lett. 11, 44-46.
6. Ye. Dinitz (1995): A compact layout of butterfly on the square grid. Technical Report 873, The Technion.
7. S. Even and A. Litman (1997): Layered cross product - a technique to construct interconnection networks. Networks 29, 219-223.
8. D.S. Greenberg, L.S. Heath, and A.L. Rosenberg (1990): Optimal embeddings of butterfly-like graphs in the hypercube. Math. Systems Theory 23, 61-77.
9. F.T. Leighton (1983): Complexity Issues in VLSI: Optimal Layouts for the Shuffle-Exchange Graph and Other Networks. MIT Press, Cambridge, MA.
10. F.T. Leighton (1992): Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes. Morgan Kaufmann, San Mateo, CA.
11. K. Mehlhorn, F.P. Preparata, and M. Sarrafzadeh (1986): Channel routing in knock-knee mode: simplified algorithms and proofs. Algorithmica, 1, 213-221.
12. R.Y. Pinter (1982): On routing two-point nets across a channel. Proc. 19th ACM-IEEE Design Automation Conf., pp. 894-902.
13. A.L. Rosenberg and L.S. Heath (1996): Graph Separators, with Applications, in preparation.
14. L. Snyder (1986): Type architectures, shared memory, and the corollary of modest potential. Ann. Rev. Comput. Sci. 1, 289-317.
15. C.D. Thompson (1979): Area-time complexity for VLSI. Proc. 11th ACM Symp. on Theory of Computing, pp. 81-88.
16. C.D. Thompson (1980): A Complexity Theory for VLSI. Ph.D. Thesis, Carnegie Mellon University.
17. D.S. Wise (1981): Compact layouts of banyan/FFT networks. In VLSI Systems and Computations (H.T. Kung, B. Sproull, and G. Steele, eds.). Computer Science Press, Rockville, MD, pp. 186-195.