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Volumn 2002-January, Issue , 2002, Pages 65-75

Reduced power consumption for MPEG decoding with LNS

Author keywords

Capacitance; Circuits; Clocks; Decoding; Digital arithmetic; DVD; Energy consumption; Frequency estimation; Multimedia systems; Transform coding

Indexed keywords

CAPACITANCE; CLOCKS; COMPUTER ARCHITECTURE; DECODING; DIGITAL ARITHMETIC; DISCRETE COSINE TRANSFORMS; ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION; FREQUENCY ESTIMATION; INVERSE TRANSFORMS; MOTION PICTURE EXPERTS GROUP STANDARDS; MULTIMEDIA SYSTEMS; NETWORKS (CIRCUITS); NUMBERING SYSTEMS; VIDEODISKS;

EID: 84948753540     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2002.1030705     Document Type: Conference Paper
Times cited : (29)

References (24)
  • 3
    • 15844369697 scopus 로고    scopus 로고
    • bmrc.berkeley.edu/research/mpeg/
    • Berkeley MPEG Tools, bmrc.berkeley.edu/research/mpeg/.
    • Berkeley MPEG Tools
  • 4
    • 0017538003 scopus 로고
    • A Fast Computational Algorithm for the Discrete Cosine Transform
    • September
    • Wen-Hsiung Chen, C. Harrison Smith and S. C. Fralick, "A Fast Computational Algorithm for the Discrete Cosine Transform," IEEE Transactions on Communications, vol. COM-25, no. 9, pp.1004-1009, September 1977.
    • (1977) IEEE Transactions on Communications , vol.COM-25 , Issue.9 , pp. 1004-1009
    • Chen, W.-H.1    Harrison Smith, C.2    Fralick, S.C.3
  • 5
    • 0013184588 scopus 로고    scopus 로고
    • Error Analysis of DCT Algorithms in Floating Point and Logarithmic Number Systems
    • Nan-Tow, Taiwan
    • C. C. Chen and Y. Y. Chen, "Error Analysis of DCT Algorithms in Floating Point and Logarithmic Number Systems," 9th VLSI Design / CAD Symposium, pp. 313-316, Nan-Tow, Taiwan, 1998.
    • (1998) 9th VLSI Design / CAD Symposium , pp. 313-316
    • Chen, C.C.1    Chen, Y.Y.2
  • 6
    • 0015004342 scopus 로고
    • Digital Filtering Using Logarithmic Arithmetic
    • 28 January
    • N. G. Kingsbury and P. J. W. Rayner, "Digital Filtering Using Logarithmic Arithmetic," Electronics Letters, vol. 7, no. 2, pp. 56-58, 28 January 1971.
    • (1971) Electronics Letters , vol.7 , Issue.2 , pp. 56-58
    • Kingsbury, N.G.1    Rayner, P.J.W.2
  • 7
    • 0000440896 scopus 로고
    • Architectural Power Analysis: The Dual Bit Type Method
    • June
    • P. Landman and J. R. Rabaey, "Architectural Power Analysis: The Dual Bit Type Method," IEEE Trans. VLSI, vol. 3, no. 2, pp. 173-187, June 1995.
    • (1995) IEEE Trans. VLSI , vol.3 , Issue.2 , pp. 173-187
    • Landman, P.1    Rabaey, J.R.2
  • 11
    • 0035152833 scopus 로고    scopus 로고
    • New Scalable DCT Computation for Resource-Constrained Systems
    • Francky Catthoor and Marc Moonen, eds., IEEE Press, Antwerp, Belgium, 26-28 Sept
    • S. Mietens, P. de With and C. Hentschel, "New Scalable DCT Computation for Resource-Constrained Systems," Proceedings of Signal Processing Systems SIPS 2001: Design and Implementation, Francky Catthoor and Marc Moonen, eds., IEEE Press, Antwerp, Belgium, pp. 285-296,26-28 Sept 2001.
    • (2001) Proceedings of Signal Processing Systems SIPS 2001: Design and Implementation , pp. 285-296
    • Mietens, S.1    De With, P.2    Hentschel, C.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.