Logarithmic number system for low-power arithmetic

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1918, Issue , 2000, Pages 285-294

  Paliouras, V ^a   Stouraitis, T ^a  

^a UNIVERSITY OF PATRAS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

NUMBERING SYSTEMS;

DIGITAL SYSTEM; EQUIVALENT-LINEAR; FIXED POINT SYSTEM; HARDWARE ARCHITECTURE; LOGARITHMIC NUMBER SYSTEM; LOW POWER ARITHMETIC; POWER SAVINGS;

NUMBER THEORY;

EID: 84872125463     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45373-3_30     Document Type: Conference Paper

References (11)

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4. W. L. Freking and K. K. Parhi, “Low power properties of Residue Number System processors,” IEEE Transactions on Circuits and Systems – Part II. To appear.
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7. T. Stouraitis, Logarithmic Number System: Theory, Analysis and Design. PhD thesis, University of Florida, 1986.
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10. V. Paliouras and T. Stouraitis, “A novel algorithm for accurate logarithmic number system subtraction,” in Proceedings of the 1996 IEEE Symposium on Circuits and Systems (ISCAS‘96), vol. 4, pp. 268–271, May 1996.
11. F. Taylor, R. Gill, J. Joseph, and J. Radke, “A 20 bit Logarithmic Number System processor,” IEEE Transactions on Computers, vol. 37, pp. 190–199, Feb. 1988.