The gate misalignment effects of the sub-threshold characteristics of sub-100 nm DG-MOSFETs

Proceedings of the IEEE Hong Kong Electron Devices Meeting

Volumn 2002-January, Issue , 2002, Pages 91-94

  Wong, Hiu Yung ^a   Shin, Kyoungsub ^a   Chan, Mansun ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Computational modeling; Computer simulation; Costs; Dielectric constant; Fabrication; Inorganic materials; Medical simulation; MOSFET circuits; Protection; Threshold voltage

Indexed keywords

ALIGNMENT; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COSTS; DIELECTRIC MATERIALS; ELECTRON DEVICES; FABRICATION; PERMITTIVITY; THRESHOLD VOLTAGE;

COMPUTATIONAL MODEL; INORGANIC MATERIALS; MEDICAL SIMULATIONS; MOSFET CIRCUITS; PROTECTION;

MOSFET DEVICES;

EID: 84948732093     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HKEDM.2002.1029164     Document Type: Conference Paper

References (6)

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3. 3 Gate Dielectrics", 2001 IEDM Tech. Dig., pp. 51-54
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6. Y. K. Choi, Doctoral Thesis, "Nanofabrication Technologies and Novel Device Structures for Nanoscale CMOS," Department of Electrical Engineering and Computer Science, University of California at Berkeley, 2001.