Branch classification to control instruction fetch in simultaneous multithreaded architectures

Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems

Volumn 2002-January, Issue , 2002, Pages 67-76

  Knijnenburg, P M W ^a   Ramirez, A ^b   Latorre, F ^b   Larriba, J ^b   Valero, M ^b  

^a LEIDEN UNIVERSITY   (Netherlands)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Computer architecture; Concurrent computing; Contracts; Degradation; Delay; Hardware; Round robin; Surface mount technology; Throughput; Yarn

Indexed keywords

COMPUTER HARDWARE; CONTRACTS; DEGRADATION; HARDWARE; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; ROUTERS; SURFACE MOUNT TECHNOLOGY; THROUGHPUT; YARN;

CLASSIFICATION MECHANISM; CONCURRENT COMPUTING; CONTROL INSTRUCTION; DELAY; HIGH UTILIZATIONS; PROCESSOR RESOURCES; ROUND ROBIN; SIMULTANEOUS MULTITHREADED ARCHITECTURES;

COMPUTER ARCHITECTURE;

EID: 84948667718     PISSN: 15373223     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWIA.2002.1035020     Document Type: Conference Paper

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