Understanding branches and designing branch predictors for high-performance microporcessors

Proceedings of the IEEE

Volumn 89, Issue 11, 2001, Pages 1610-1620

  Evers, Marius ^a   Yeh, Tse Yu ^b  

^a ADVANCED MICRO DEVICES   (United States)

^b Broddcom Corporation   (United States)

Author keywords

Branch prediction; Speculation

Indexed keywords

EID: 4644294518     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.964441     Document Type: Article

References (26)

1. B. Calder, D. Grunwald, and j. Emer, A system level perspective on branch architecture performance, ir. 28th ACM/IEEE Int. Symp. Microarchitecture, 1995.
2. Welcome to SPEC. The Standard Performance Evaluation Corporation. [Online]. Available: http://www.specbench.org/
3. T.-Y. Yeh, Two-level adaptive branch prediction and instruction fetch mechanisms for high performance superscalar processors, Ph.D. dissertation. Univ. Michigan, Ann Arbor, 1993.
4. D. Kaeli and P. Emma, Branch history table predictions of moving target branches due to subroutine returns, in ISili Anna. Int. Symp. Computer Architecture, 1991.
5. P.-Y. Chang, E. Hao, and Y. N. Patt, Predicting indirect jumps using a target cache, in Proc. 24th Annu. In!. Symp. Computer Architecture, 1997.
6. VI. Evers, Improving branch prediction by understanding branch behavior, Ph.D. dissertation, Univ. Michigan. Ann Arbor, 2000.
7. M. Evers, S. .1. Patel, R. S. Chappell, and Y. N. Patt, An analysis of correlation and predictability: What makes two-level branch predictors work, in 25th Annu. Int. Symp. Computer Architecture, 1998.
8. J. A. Fisher and S. M. Freudenberger, Predicting conditional branch directions from previous runs of a program, in 5th Int. Conf. Architectural Support for Programming Languages and Operating Systems, 1992.'
9. j. E. Smith, A study of branch prediction strategies, in 8th Int. Symp, Computer Architecture, 1981.
10. T.-Y. Yeh and Y. N. Patt, Two-level adaptive branch prediction, in 24th ACM/IEEE Int. Symp. Microarchitec.'ure, 1991.
11. _, Alternative implementations of two-level adaptive branch prediction, in 19th Annu. Int. Symp. Computer Architecture, 1992.
12. S. McFarling, Combining branch predictors, Digital Equipment Corporation, WRL Tech. Note TX-36, 1993.
13. R. Nair, Dynamic path-based branch correlation, in 28th AC.WIEEE Int. Symp. Micwarchiteclure, 1995.
14. J. Stark, M Evers, and Y. N. Patt, Variable length path branch prediction, in Proc. 8th Int. Conf. Architectural Support for Programming Languages ana Operating Systems, 1998.
15. T. Juan, S. Sunjeevan, and J. J. Navarro, Dynamic history-length fitting: A third level of adaptivity for branch prediction, in 25th Annu. Int. Symp. Computer Architecture, 199S.
16. P.-Y. Chang, M. Evers, and Y. N. Patt, Improving branch prediction accuracy by reducing pattern history table interference, in Proc. Int. Conf. Parallel Architectures and Compilation Techniques, S996.
17. E. Sprangle, R. S. Chappell, M. Alsiip, and Y. N. Patt, The agree predictor: A mechanism for reducing negative branch history interference, in P roc. 24th Anna. Int. Svntp. Computer Architecture, 1991.
18. P. Michaud, A. Seznec, and R. Uhlig, Trading conflict and capacity aliasing in conditional branch predictors, in 24ih Aiinu. Int. Symp. Computer Architecture, 1997.
19. C.-C. Lee, I.-C. K. Chen, and T. X. Mudge, The bi-mocle branch predictor, in 30th ACM/IEEE Int. Sym.p, Microarchitecture, 1997.
20. [201 C.-C. Lee, Optimizing high performance dynamic branch predictors, Ph.D. dissertation, Univ. Michigan. Ann Arbor, 1997.
21. [21 ] P.-Y. Chang, E. Hao, and Y. \. Pali, Alternative implementations of hybrid branch predictors, in 2Sth ACM/IEEE Int. Symp. Micrvarchnectnre, Nov. 1995.
22. M. Evers, P.-Y. Chaag, and Y. N. Patt, Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches, in 23ra Anna, lui, Symp. Computer Architecture, 1996.
23. D. Grunwald, D. Lindsay, and B. Zorn, Static methods in hybrid branch prediction, in Proc. 1998 ACM/IEEE Conf. Parallel Architectures m.d Compilation Techniques. 199S.
24. D. A. Jimenez, S. W. Keckler, and L. Calvin, The impact of delay on the design of branch predictors, ia 33rd ACM/IEEE Int. Symp. .Vlicroarchiti'ciure. Dec. 200Udie;.
25. L. Gwcnnap, Digital 21264 sets new standard, Microprocessor Rep., 1996.
26. A. Seznec, S. Jourdan, P. Sainrat, and p. Michaud, Multiple-block ahead branch predictors, in Proc. 7th Int. Conf. Architectural Supportfor Programming Languages and Operating Systems, 1996.