-
1
-
-
85008008190
-
2 mb spram (spin-transfer torque ram) with bit-by-bit bi-directional current write and parallelizing-direction current read
-
T. Kawahara et al. 2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. IEEE JSSC, 43(1):109-120, 2008.
-
(2008)
IEEE JSSC
, vol.43
, Issue.1
, pp. 109-120
-
-
Kawahara, T.1
-
2
-
-
71049160813
-
Low-current perpendicular domain wall motion cell for scalable high-speed mram
-
S. Fukami et al. Low-Current Perpendicular Domain Wall Motion Cell for Scalable High-Speed MRAM. In Proc. VLSI Tech. Symp., pages 230-231, 2009.
-
(2009)
Proc. VLSI Tech. Symp
, pp. 230-231
-
-
Fukami, S.1
-
3
-
-
0043197342
-
Nanocomputing by field-coupled nanomagnets
-
G. Csaba et al. Nanocomputing by field-coupled nanomagnets. IEEE TNANO, 1(4):209-213, 2002.
-
(2002)
IEEE TNANO
, vol.1
, Issue.4
, pp. 209-213
-
-
Csaba, G.1
-
4
-
-
24644506125
-
Magnetic Domain-Wall Logic
-
D. A. Allwood et al. Magnetic Domain-Wall Logic. Science, 309(5741):1688-1692, 2005.
-
(2005)
Science
, vol.309
, Issue.5741
, pp. 1688-1692
-
-
Allwood, D.A.1
-
5
-
-
84863537067
-
MLogic: Ultra-low voltage non-volatile logic circuits using STT-MTJ devices
-
D. Morris et al. mLogic: Ultra-low voltage non-volatile logic circuits using STT-MTJ devices. In Proc. DAC, pages 486-491, 2012.
-
(2012)
Proc. DAC
, pp. 486-491
-
-
Morris, D.1
-
6
-
-
77950864797
-
Proposal for an all-spin logic device with built-in memory
-
B. Behin-Aein et al. Proposal for an all-spin logic device with built-in memory. Nature Nanotechnology, 5(4):266-270, 2010.
-
(2010)
Nature Nanotechnology
, vol.5
, Issue.4
, pp. 266-270
-
-
Behin-Aein, B.1
-
7
-
-
84889633757
-
Overview of beyond-CMOS devices and a uniform methodology for their benchmarking
-
D. E. Nikonov and I. A. Young. Overview of beyond-CMOS devices and a uniform methodology for their benchmarking. Proceedings of the IEEE, 101(12):2498-2533, 2013.
-
(2013)
Proceedings of the IEEE
, vol.101
, Issue.12
, pp. 2498-2533
-
-
Nikonov, D.E.1
Young, I.A.2
-
9
-
-
78649938802
-
An architecture for fault-tolerant computation with stochastic logic
-
W. Qian et al. An architecture for fault-tolerant computation with stochastic logic. IEEE Trans. Computers, 60(1):93-105, 2011.
-
(2011)
IEEE Trans. Computers
, vol.60
, Issue.1
, pp. 93-105
-
-
Qian, W.1
-
10
-
-
84891879851
-
Survey of stochastic computing
-
A. Alaghi and J. Hayes. Survey of stochastic computing. ACM TECS, 12(2s):92:1-92:19, 2013.
-
(2013)
ACM TECS
, vol.12
, Issue.2
, pp. 921-9219
-
-
Alaghi, A.1
Hayes, J.2
-
11
-
-
84906807372
-
StoRM: A stochastic recognition and mining processor
-
V. Chippa et al. StoRM: A Stochastic Recognition and Mining Processor. In Proc. ISLPED, pages 39-44, 2014.
-
(2014)
Proc. ISLPED
, pp. 39-44
-
-
Chippa, V.1
-
12
-
-
0003133883
-
Probabilistic logics and the synthesis of reliable organisms from unreliable components
-
J. Von Neumann. Probabilistic logics and the synthesis of reliable organisms from unreliable components. Automata Studies, pages 43-98, 1956.
-
(1956)
Automata Studies
, pp. 43-98
-
-
Von Neumann, J.1
-
13
-
-
0035440487
-
Stochastic neural computation I: Computational elements
-
B.D. Brown and H.C. Card. Stochastic neural computation I: Computational elements. IEEE Trans. Computers, 50(9):891-905, 2001.
-
(2001)
IEEE Trans. Computers
, vol.50
, Issue.9
, pp. 891-905
-
-
Brown, B.D.1
Card, H.C.2
-
14
-
-
54949135258
-
Fully parallel stochastic LDPC decoders
-
S. Tehrani et al. Fully parallel stochastic LDPC decoders. IEEE Trans. Signal Processing, 56(11):5692-5703, 2008.
-
(2008)
IEEE Trans. Signal Processing
, vol.56
, Issue.11
, pp. 5692-5703
-
-
Tehrani, S.1
-
15
-
-
84906540967
-
Generating true random numbers using on-chip complementary polarizer spin-transfer torque magnetic tunnel junctions
-
X. Fong, M. C. Chen, and K. Roy. Generating true random numbers using on-chip complementary polarizer spin-transfer torque magnetic tunnel junctions. In Proc. DRC, pages 103-104, 2014.
-
(2014)
Proc. DRC
, pp. 103-104
-
-
Fong, X.1
Chen, M.C.2
Roy, K.3
-
16
-
-
84945931751
-
A magnetic tunnel junction based true random number generator with conditional perturb and real-time output probability tracking
-
A Magnetic Tunnel Junction Based True Random Number Generator with Conditional Perturb and Real-Time Output Probability Tracking. In Proc. IEDM, 2014.
-
(2014)
Proc. IEDM
-
-
-
17
-
-
84879581874
-
Design of ultra high density and low power computational blocks using nano-magnets
-
M. Sharad et al. Design of ultra high density and low power computational blocks using nano-magnets. In Proc. ISQED, 2013.
-
(2013)
Proc. ISQED
-
-
Sharad, M.1
-
18
-
-
79961205210
-
Low-power functionality enhanced computation architecture using spin-based devices
-
C. Augustine et al. Low-power functionality enhanced computation architecture using spin-based devices. In Proc. NANOARCH, pages 129-136, 2011.
-
(2011)
Proc. NANOARCH
, pp. 129-136
-
-
Augustine, C.1
-
19
-
-
79953879378
-
Switching energy-delay of all spin logic devices
-
B. Behin-Aein et al. Switching energy-delay of all spin logic devices. APL, 98(12):123510-123510-3, 2011.
-
(2011)
APL
, vol.98
, Issue.12
, pp. 123510-1235103
-
-
Behin-Aein, B.1
|