A novel design of a two operand normalization circuit

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 1, 1998, Pages 173-176

  Antelo, Elisardo ^a   Bóo, Montserrat ^a   Bruguera, Javier D ^a   Zapata, Emilio L ^b  

^a UNIVERSITY OF SANTIAGO DE COMPOSTELA   (Spain)

^b UNIVERSITY OF MÁLAGA   (Spain)

Author keywords

Digital VLSI design; Floating point operations; Leading zero detector circuit; Normalization

Indexed keywords

DETECTOR CIRCUITS; DIGITAL ARITHMETIC; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS;

COORDINATE ROTATION DIGITAL COMPUTER (CORDIC) PROCESSORS; NORMALIZATION CIRCUITS;

VLSI CIRCUITS;

EID: 0032026422     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.661260     Document Type: Article

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