Yield analysis for repairable embedded memories

Proceedings of the European Test Workshop

Volumn 2003-January, Issue , 2003, Pages 35-40

  Sehgal, A ^c   Dubey, A ^d,e   Marinissen, E J ^a   Wouters, C ^b   Vranken, H ^a   Chakrabarty, K ^c  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

^c USA   (United States)

^d INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

^e TEXAS INSTRUMENTS   (India)

Author keywords

Algorithm design and analysis; Automatic testing; Circuit faults; Circuit testing; Heuristic algorithms; Manufacturing industries; Partitioning algorithms; Redundancy; Silicon; Very large scale integration

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; DEFECT DENSITY; ELECTRIC NETWORK ANALYSIS; HEURISTIC ALGORITHMS; MEMORY ARCHITECTURE; REDUNDANCY; SILICON; VLSI CIRCUITS;

ALGORITHM DESIGN AND ANALYSIS; CIRCUIT FAULTS; CIRCUIT TESTING; MANUFACTURING INDUSTRIES; PARTITIONING ALGORITHMS;

INTEGRATION TESTING;

EID: 84942852923     PISSN: 15301877     EISSN: 15581780     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.2003.1231666     Document Type: Conference Paper

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