Cycle-accurate energy measurement and high-level energy characterization of FPGAs

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2003-January, Issue , 2003, Pages 267-272

  Lee, Hyung Gyu ^a   Nam, Sungyuep ^a   Chang, Naehyuck ^a  

^a Seoul National University   (South Korea)

Author keywords

Design automation; Energy consumption; Energy measurement; Field programmable gate arrays; Logic circuits; Logic design; Logic devices; Programmable logic arrays; Resource management; System on a chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CHARACTERIZATION; COMPUTER AIDED DESIGN; COMPUTER AIDED LOGIC DESIGN; DESIGN; ELECTRIC POWER MEASUREMENT; ENERGY UTILIZATION; LOGIC CIRCUITS; LOGIC DESIGN; LOGIC DEVICES; LOGIC GATES; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP;

DESIGN AUTOMATIONS; ENERGY CHARACTERIZATION; PROGRAMMABLE LOGIC ARRAY; RESOURCE MANAGEMENT; RESOURCE UTILIZATIONS; SYSTEM ON A CHIP; SYSTEM ON CHIP DESIGN; TRANSITION ACTIVITY;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84942118573     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2003.1194744     Document Type: Conference Paper

References (15)

1. S. Wenande and R. Chidester, "Xilinx takes power analysis to new levels with XPower," Xcell Journal Online, pp. 26 - 27, Fall - Winter 2001.
2. E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. Sangiovanni, "Sequential circuit design using synthesis and optimization," in Proceddings fo the IEEE International Conference on Computer Design, pp. 328 - 333, october 1992.
3. B. Lin and H. D. Man, "Low-power driven technology mapping under timing constraints," in IEEE International Conference on Computer Design, pp. 421 - 427, October 1993.
4. C.-S. Chen, T. Hwang, and C. L. Liu, "Low power FPGA design - A re-engineering approach," in Proceeding of DAC 1997, pp. 656 - 661, June 1997.
5. V. George, H. Zhang, and J. Rabaey, "The design of a low energy FPGA," in Proceedings of ISLPED 1999, pp. 188 - 193, August 1999.
6. G. C. Cardarilli, A. D. Re, A. Nannarelli, and M. Re, "Power characterization of digital filters implemented on FPGA," in Proceedings of the International Symposium on Circuit and System, vol. 5, pp. 801 - 804, 2002.
7. Altera Corporation, "Power consumption comparison: APEX 20K vs. Virtex devices," Altera Technical Brief, October 1999.
8. T. Osmulski, J. T. Mudhring, B. Veale, J. M. West, H. Li, S. Vanichayobon, S.-H. Ko, J. K. Antonio, and S. K. Dhall, "A probalilistic power prediction tool for the Xilinx 4000-series FPGA," in Proceedings of the 5th International Workshop on Embedded/Distributed HPC Systems and Application, pp. 776 - 783, May 2000.
9. E. A.Kusse, "Analysis and circuit design for lowpower programmable logic modules," in Master's thesis, Dept. of Electrical Engineering and Computer Science, University of Califonia at Berkely, 1998.
10. B. Kumthekar, L. M. ii, and F. Somenzi, "Power optimization of FPGA-based designs without rewiring," in Proceedings of IEE Computers and Digital Techniques, vol. 147, pp. 167 - 174, May 2000.
11. Altera Corporation, "Evaluation power for Altera devices," Altera Application Note, July 2001.
12. N. Chang, K. Kim, and H. G. Lee, "Cycle-accurate energy consumption measurement and analysis: Case study of ARM7TDMI," IEEE Transactions on VLSI Systems, vol. 10, pp. 146 - 154, April 2002.
13. M. J. Alexander, "Power optimization for FPGA look-up tables," in Proceedings of ISPD, pp. 156 - 162, 1997.
14. K. Roy, "Power-dissipation driven FPGA place and route under timing constraints," IEEE Transaction On Circiuts And Systems, vol. 46, pp. 634 - 637, May 1999.
15. Y. Joo, Y. S. Choi, H. Shim, H. G. Lee, K. Kim, and N. Chang, "Energy exploration and reduction of SDRAM memory systems," in Proceedings of DAC 2002, pp. 892 - 897, June 2002.