Behavioral synthesis of datapaths with low leakage power

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2002, Pages IV/699-IV/702

  Gopalakrishnan, Chandramouli ^a   Katkoori, Srinivas ^a  

^a University of South Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC POTENTIAL; OPTIMIZATION; TECHNOLOGY;

BEHAVIORAL SYNTHESIS; DATAPATHS; LOW LEAKAGE POWER;

CMOS INTEGRATED CIRCUITS;

EID: 0036287826     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1010552     Document Type: Article

References (8)

1. Dual-threshold voltage techniques for low-power digital circuits
2. IV power supply highspeed digital circuit technology with multi-threshold voltage CMOS
3. A gate-level leakage power reduction method for ultra-low-power CMOS circuits
4. Leakage power reduction in low-voltage CMOS design
5. Leakage power analysis and reduction during behavioral synthesis
6. Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories
7. Design considerations and tools for low-voltage digital system design
8. FACET: A procedure for the automated synthesis of digital systems