Architectural approaches to reduce leakage energy in caches

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages

  Tadas, Shashikiran H ^a   Chakrabarti, Chaitali ^a  

^a Arizona State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; COMPUTER HARDWARE; COMPUTER SIMULATION; ELECTRIC LOSSES; ELECTRIC POWER SUPPLIES TO APPARATUS; MATHEMATICAL MODELS; PERFORMANCE;

CACHE SUBBANK; LEAKAGE ENERGY; SOFTWARE PACKAGE SPECJVM98; SUBBANKED CACHE STRUCTURE;

CACHE MEMORY;

EID: 0036286893     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. An energy efficient high performance deep-submicron instruction cache
2. Selective cache ways: On-demand cache resource allocation
3. Cache decay: Exploiting generational behavior to reduce cache leakage power
4. Shade: A fast instruction-set simulator for execution profiling
5. Run-time cache bypassing
6. An integrated cache timing and power model